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path: root/drivers/memory/tegra/tegra30-emc.c
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2020-06-22memory: tegra30-emc: Poll EMC-CaR handshake instead of waiting for interruptDmitry Osipenko
The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-22memory: tegra: Make debugfs permissions human-readableDmitry Osipenko
Replace the symbolic permissions with octals in order to make them readable. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-11memory: tegra: Correct debugfs clk rate-range on Tegra30Dmitry Osipenko
Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8cee32b40040 ("memory: tegra: Implement EMC debugfs interface on Tegra30") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10memory: tegra30-emc: Correct error message for timed out auto calibrationDmitry Osipenko
The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10memory: tegra30-emc: Firm up hardware programming sequenceDmitry Osipenko
Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10memory: tegra30-emc: Firm up suspend/resume sequenceDmitry Osipenko
The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Implement EMC debugfs interface on Tegra30Thierry Reding
A common debugfs interface is already available on Tegra20, Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-18memory: tegra30-emc: Fix panic on suspendDmitry Osipenko
Trying to suspend driver results in a crash if timings aren't available in device-tree. Reported-by: Jon Hunter <jonathanh@nvidia.com> Fixes: e34212c75a68 ("memory: tegra: Introduce Tegra30 EMC driver") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Introduce Tegra30 EMC driverDmitry Osipenko
Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>