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The V4L2 core sets the format description and flags for the driver in order
to ensure consistent naming.
So drop the strscpy of the description in drivers. Also remove any
description strings in driver-internal structures since those are
no longer needed.
And in am437x-vpfe.c drop an unnecessary f->type assignment in
vpfe_enum_fmt().
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[hverkuil-cisco@xs4all.nl: addressed some small suggestions from Laurent]
Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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Use codespell to fix lots of typos over frontends.
Manually verified to avoid false-positives.
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Houlong Wei <houlong.wei@mediatek.com>
Reviewed-by: Yong Deng <yong.deng@magewell.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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In formats table the entry for CFA pattern "rggb" has GRBG fourcc.
This patch fixes it.
Signed-off-by: Mirco Di Salvo <mirco.disalvo@iit.it>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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SPDX-License-Identifier is used for the Xilinx Video IP and
related drivers.
[Added drivers/media/platform/xilinx/Kconfig]
[Added drivers/media/platform/xilinx/Makefile]
[Added include/dt-bindings/media/xilinx-vip.h]
Signed-off-by: Dhaval Shah <dhaval23031987@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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Xilinx platforms have no hardwired video capture or video processing
interface. Users create capture and memory to memory processing
pipelines in the FPGA fabric to suit their particular needs, by
instantiating video IP cores from a large library.
The Xilinx Video IP core is a framework that models a video pipeline
described in the device tree and expose the pipeline to userspace
through the media controller and V4L2 APIs.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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