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path: root/drivers/media/i2c
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2021-01-12media: ov5647: Program mode at s_stream(1) timeJacopo Mondi
Rename __sensor_init() function to ov5647_set_mode() as the function is a regular one and the double underscores prefix shall be removed, and then move it to program the mode at s_stream(1) time, not at sensor power up. Break out from __sensor_init() the stream_off() operation call at sensor power up to coax the lanes in LP-11 state. Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Fix return value from read/writeJacopo Mondi
The ov5647_read()/ov5647_write() return in case of success the number of bytes read or written respectively. This requires callers to check if the return value is less than zero to detect an error. Unfortunately, in several places, callers directly return the result of a read/write call, causing issues when the returned valued is checked to be different from zero to detect an error. Fix this by returning zero if i2c_master_send() and i2c_master_read() return a positive value (the number of bytes written or read). Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Replace license with SPDX identifierJacopo Mondi
Replace the boilerplate license text with the SPDX identifier. Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Fix style issuesJacopo Mondi
The driver has some obvious style issues which are worth fixing before expanding the driver capabilities. Fix: - Variable declaration order - Function parameters alignment - Multi-line comments and spurious line breaks - Use lowercase for hexadecimal values - > 80 cols lines Cosmetic change, no functional changes intended. Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Fix format initializationJacopo Mondi
The driver currently support a single format. Fix its initialization to use the only supported resolution. Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Add set_fmt and get_fmt calls.Dave Stevenson
There's no way to query the subdevice for the supported resolutions. Add set_fmt and get_fmt implementations. Since there's only one format supported set_fmt does nothing and get returns single format. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org> Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Add support for non-continuous clock modeDave Stevenson
Add support for optional non-continuous clock mode to the ov5647 sensor driver. Non-continuous clock saves a small amount of power and on some SoCs is easier to interface with. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org> Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: ov5647: Add support for PWDN GPIO.Dave Stevenson
Add support for an optional GPIO connected to PWDN on the sensor. This allows the use of hardware standby mode where internal device clock and circuit activities are halted. Please note that power is off when PWDN is high. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org> Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-12media: i2c: imx219: take lock in imx219_enum_mbus_code/frame_sizeHans Verkuil
These two functions did not take the imx219->mutex lock, but imx219_get_format_code checks that a lock is taken, so it issues a warning: [ 8.738717] WARNING: CPU: 2 PID: 60 at drivers/media/i2c/imx219.c:653 imx219_get_format_code+0xac/0xc0 [ 8.748113] Modules linked in: [ 8.751214] CPU: 2 PID: 60 Comm: kworker/2:1 Tainted: G W 5.8.0-rc1-arm64 #148 [ 8.759821] Hardware name: NVIDIA Jetson TX1 Developer Kit (DT) [ 8.765806] Workqueue: events deferred_probe_work_func [ 8.771003] pstate: 60000005 (nZCv daif -PAN -UAO BTYPE=--) [ 8.776635] pc : imx219_get_format_code+0xac/0xc0 [ 8.781390] lr : imx219_get_format_code+0xa8/0xc0 [ 8.786143] sp : ffff800012a538f0 [ 8.789495] x29: ffff800012a538f0 x28: ffff800012838e90 [ 8.794867] x27: ffff0000f28c5800 x26: ffff800011161c68 [ 8.800237] x25: ffff0000f2a5a3f8 x24: 0000000000000018 [ 8.805605] x23: ffff0000f284ef18 x22: ffff0000f2a5a080 [ 8.810974] x21: ffff0000f284ff00 x20: ffff0000f2a5a080 [ 8.816343] x19: 000000000000300f x18: 00000000ffffffff [ 8.821712] x17: ffff800011c77268 x16: 00000000000040d7 [ 8.827081] x15: 00000000000040d8 x14: 0000000000000000 [ 8.832451] x13: 00000000000040d4 x12: ffff800011d19300 [ 8.837819] x11: 00000000000208c0 x10: 0000000000000004 [ 8.843188] x9 : 000000003baa2ecd x8 : 000000008b3f9c73 [ 8.848558] x7 : 0000000000000008 x6 : 0000000000000034 [ 8.853929] x5 : 0000000000000000 x4 : 0000000000000001 [ 8.859297] x3 : ffff800010a2a8a8 x2 : ffff0000f84a8000 [ 8.864666] x1 : 0000000000000000 x0 : 0000000000000000 [ 8.870034] Call trace: [ 8.872515] imx219_get_format_code+0xac/0xc0 [ 8.876921] imx219_enum_mbus_code+0x38/0x60 [ 8.881241] call_enum_mbus_code+0x50/0x70 [ 8.885387] tegra_vi_graph_notify_complete+0x290/0x5e8 [ 8.890670] v4l2_async_notifier_try_complete.part.0+0x48/0x68 [ 8.896563] v4l2_async_register_subdev+0x100/0x1c0 [ 8.901497] v4l2_async_register_subdev_sensor_common+0x70/0xf0 [ 8.907477] imx219_probe+0x590/0x728 [ 8.911184] i2c_device_probe+0xe4/0x2b0 [ 8.915151] really_probe+0xd8/0x330 [ 8.918768] driver_probe_device+0x58/0xb8 [ 8.922909] __device_attach_driver+0x84/0xc8 [ 8.927315] bus_for_each_drv+0x78/0xc8 [ 8.931193] __device_attach+0xe4/0x140 [ 8.935072] device_initial_probe+0x14/0x20 [ 8.939301] bus_probe_device+0x9c/0xa8 [ 8.943179] deferred_probe_work_func+0x74/0xb0 [ 8.947759] process_one_work+0x2c4/0x740 [ 8.951813] worker_thread+0x4c/0x430 [ 8.955518] kthread+0x158/0x178 [ 8.958786] ret_from_fork+0x10/0x1c [ 8.962401] irq event stamp: 63536 [ 8.965846] hardirqs last enabled at (63535): [<ffff800010082398>] el1_irq+0xd8/0x180 [ 8.973846] hardirqs last disabled at (63536): [<ffff8000100a6484>] do_debug_exception+0x16c/0x258 [ 8.982895] softirqs last enabled at (63534): [<ffff800010080d4c>] _stext+0x54c/0x594 [ 8.990896] softirqs last disabled at (63525): [<ffff8000100c8350>] irq_exit+0x100/0x138 [ 8.999066] ---[ end trace ebfbcd84b75ef921 ]--- [ 9.004354] ------------[ cut here ]------------ Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-07media: ccs: Get static data version minor correctlySakari Ailus
Fix obtaining CCS static data version minor part correctly. Instead, the upper 8 bits were obtained from the major version number. Fixes: a6b396f410b1 ("media: ccs: Add CCS static data parser library") Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-07media: ccs-pll: Fix link frequency for C-PHYSakari Ailus
The highest fundamental frequency signal for C-PHY is half of the symbol rate which is similar to D-PHY. Take this into account in ccs-pll. Also remove the outdated comment. Fixes: 8030aa4f9c51 ("media: ccs-pll: Add C-PHY support") Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Add support for obtaining C-PHY configuration from firmwareSakari Ailus
Try parsing the firmware also as C-PHY. Do this only after D-PHY as older firmware may not explicitly specify bus-type in which case D-PHY is the default. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus
Print pixel rates on CSI-2 bus as well as in pixel array as the variation allowed in PLL capabilities makes this non-trivial to figure out otherwise. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Print written register valuesSakari Ailus
This helps debugging register writes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Add support for DDR OP SYS and OP PIX clocksSakari Ailus
Support dual data rate operational system and pixel clocks by conveying the flags to the PLL calculator and updating how the link rate is calculated. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus
Add support for dual data rate operational system and pixel clocks. This is implemented using two PLL flags. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Dual PLL supportSakari Ailus
Add support for sensors that either require dual PLL or support single or dual PLL but use dual PLL as default. Use sensor default configuration for sensors that support both modes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus
Add support for sensors that have separate VT and OP domain PLLs. This support is trivial in the sense that it aims for the same VT pixel rate than that on the CSI-2 bus. The vast majority of sensors is better supported by higher frequencies in VT domain in binned and possibly scaled configurations. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus
Separate VT divisor limit calculation from the rest of the VT PLL branch calculation. This way it can be used for dual PLL support as well. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus
The PLL calculator only searched even total divisor values apart from one, but this is wrong: the total divisor is odd in cases where system divisor is one. Fix this by including odd total PLL values where system divisor is one to the search. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus
Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after all. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus
Refactor bounds checks so that the caller can decide what to check. This allows doing the checks early, when the values are available. This also adds front OP PLL configuration and limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus
Print information on PLL tree configuration based on the flags. This also adds support for printing dual PLL trees, and better separates between OP and VT PLL trees. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus
Better separate OP PLL branch calculation from VT branch calculation. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus
Some sensors support derating (VT domain speed faster than OP) or overrating (VT domain speed slower than OP). While this was supported for the driver, the hardware support for the feature was never verified. Do that now, and for those devices without that support, VT and OP speeds have to match. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus
Split off the VT sub clock tree calculation from the rest, into its own function. Also call the op_pll_fr argument pll_fr, since soon these may not be OP tree values. This paves way for additional features in the future such as dual PLL support. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus
Add C-PHY support for the CCS PLL calculator. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus
Add sanity checks for fields that could cause division by zero. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus
Flexible OP PLL pixel clock divider allows a higher OP pixel clock than what the bus can transfer. This generally makes it easier to select pixel clock dividers. This changes how the pixel rate on the bus and minimum VT divisor are calculated, as the pixel rate is no longer directly determined by the OP pixel clock and the number of the lanes. Also add a sanity check for sensors that do not support flexible OP PLL pixel clock divider. This could have caused the PLL calculator to come up with an invalid configuration for those devices. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus
The l parameter defines the number of clock cycles to process a single pixel per OP lane. It is calculated based on a new register op_bits_per_lane. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus
CCS allows odd PLL dividers other than 1, granted that the corresponding capability bit is set. Support this both in the PLL calculator and the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus
Add support for decoupled OP domain clock calculation. This means that the number of VT and OP domain clocks are no longer dependent on the number of CSI-2 lanes in the lane speed mode. The support also replaces the existing quirk flag to calculate OP domain clocks per lane. Also support decoupled OP domain calculation in the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Add support for lane speed modelSakari Ailus
Convey the relevant PLL flags to the PLL calculator. Also the lane speed model affects how the link rate is calculated on the CSI-2 bus, as the rate is total of all lanes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus
CCS PLL includes a capability to calculate the VT clocks on per-lane basis. Add support for this feature. Move calculation of the pixel rate on the CSI-2 bus early in the function as everything needed to calculate it is already available. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus
Use uint32_t instead of unsigned int for a variable that contains explicitly 32-bit numbers. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus
The additional multiplier (for higher VT timing) of the PLL multiplier was checked against the upper limit but the result was rounded up, possibly producing too high additional multiplier. Round down instead to keep within hardware limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus
The comment is about minimum PLL multiplier but the related check really deals with the maximum PLL multiplier. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus
The external clock frequency times the PLL multiplier may exceed the value range of 32-bit unsigned integers. Instead perform the same calculation y using two divisions. The result has some potential to be different, but that's ok: this number is used to limit the range of pre-PLL divisors to find optimal values. So the effect of the rare case of a different result here would mean an invalid pre-PLL divisor is tried. That will be found out a little later in any case. Also guard against dividing by zero if the external clock frequency is higher than the maximum OP PLL output clock --- a rather improbable case. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus
The lower bound of the pre-PLL divider was calculated based on OP SYS clock frequency which is also affected by the OP SYS clock divider. This is wrong. The right clock frequency is that of the PLL output clock. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus
The OP system clock frequency defines the CSI-2 bus clock frequency, not the PLL output clock frequency. Both values were overwritten in the end, but the wrong limit value was used for the OP system clock frequency, possibly leading to too high frequencies being used. Also remove now duplicated calculation of OP system clock frequency later in the PLL calculator. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Use the BIT macroSakari Ailus
Use the BIT macro for setting individual bits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus
The CCS pll is used by the CCS driver at the moment, but documenting the interface makes sense. It's non-trivial and the calculator could be used elsewhere. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus
This way the struct will use less memory, with better packing and no waste due to unsigned long. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus
Differentiate between CSI-2 D-PHY and C-PHY. This does not yet include support for C-PHY. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus
The parallel bus PLL calculation has no users. Remove it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus
The VT divisor search can be ended if we've already found the value that corresponds exactly the total divisor, as there are no better (lower) values available. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus
Use the correct video timing divisor to calculate the SYS divisor. Instead of the current value, the minimum was used. This could have resulted in a too low SYS divisor. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus
The CCS spec supports a lot of variation in the PLL. Split the PLL in front and back parts to better prepare for supporting it. Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include "clk" in the name). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus
pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to divide it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Fix return value from probeSakari Ailus
rval wasn't set, resulting in probe returning zero instead of an error. Fixes: de10c1619c48 ("[media] smiapp: Get clock rate if it's not available through DT") Reported-by: Zhang Changzhong <zhangchangzhong@huawei.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-03 23:45:48 +0000