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path: root/drivers/iio/adc/ad4695.c
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2025-01-13Merge 6.13-rc4 into char-misc-nextGreg Kroah-Hartman
We need the IIO fixes in here as well, and it resolves a merge conflict in: drivers/iio/adc/ti-ads1119.c Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-07iio: adc: ad4695: move dt-bindings headerDavid Lechner
Move the dt-bindings header file to the include/dt-bindings/iio/adc/ directory. ad4695 is an ADC driver, so it should be in the adc/ subdirectory for better organization. Previously, it was in the iio/ subdirectory. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20241113-iio-adc-ad4695-move-dt-bindings-header-v1-1-aba1f0f9b628@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-12-07iio: adc: ad4695: fix buffered read, single sample timingsTrevor Gamblin
Modify ad4695_buffer_preenable() by adding an extra SPI transfer after each data read to help ensure that the timing requirement between the last SCLK rising edge and the next CNV rising edge is met. This requires a restructure of the buf_read_xfer array in ad4695_state. Also define AD4695_T_SCK_CNV_DELAY_NS to use for each added transfer. Without this change it is possible for the data to become corrupted on sequential buffered reads due to the device not properly exiting conversion mode. Similarly, make adjustments to ad4695_read_one_sample() so that timings are respected, and clean up the function slightly in the process. Fixes: 6cc7e4bf2e08 ("iio: adc: ad4695: implement triggered buffer") Co-developed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Tested-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20241113-tgamblin-ad4695_improvements-v2-1-b6bb7c758fc4@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-09-03iio: adc: ad4695: implement calibration supportDavid Lechner
The AD4695 has a calibration feature that allows the user to compensate for variations in the analog front end. This implements this feature in the driver using the standard `calibgain` and `calibbias` attributes. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20240820-ad4695-gain-offset-v1-2-c8f6e3b47551@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-09-03iio: adc: ad4695: add 2nd regmap for 16-bit registersDavid Lechner
The AD4695 and similar chips have some multibyte registers that have to be read/written in a single operation. So we need to add a 2nd regmap for these registers. These registers are removed from the 8-bit regmap allowable ranges and AD4695_MAX_REG is dropped since it would be ambiguous now. debugfs register access is also updated to automatically use the correct regmap depending on the register address. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20240820-ad4695-gain-offset-v1-1-c8f6e3b47551@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-08-17iio: adc: ad4695: implement triggered bufferDavid Lechner
This implements buffered reads for the ad4695 driver using the typical triggered buffer implementation, including adding a soft timestamp channel. The chip has 4 different modes for doing conversions. The driver is using the advanced sequencer mode since that is the only mode that allows individual configuration of all aspects each channel (e.g. bipolar config currently and oversampling to be added in the future). Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20240813-iio-adc-ad4695-buffered-read-v2-1-9bb19fc1924b@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-08-03iio: adc: ad4695: Add driver for AD4695 and similar ADCsDavid Lechner
This is a new driver for Analog Devices Inc. AD4695 and similar ADCs. The initial driver supports initializing the chip including configuring all possible LDO and reference voltage sources as well as any possible voltage input channel wiring configuration. Only the 4-wire SPI wiring mode where the CNV pin is tied to the CS pin is supported at this time. And reading sample data from the ADC can only be done in direct mode for now. Co-developed-by: Ramona Gradinariu <ramona.gradinariu@analog.com> Signed-off-by: Ramona Gradinariu <ramona.gradinariu@analog.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Link: https://patch.msgid.link/20240711-iio-adc-ad4695-v4-2-c31621113b57@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>