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path: root/drivers/gpu/drm
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2016-09-15drm/msm/mdp4: Fix issue with LCDC/LVDS port parsingArchit Taneja
The LVDS port is the first in the list of the output ports in MDP4. The driver assumed that if the port and its corresponding endpoint is defined, then there should be a panel node too. This isn't necessary since boards may not really use a LVDS panel. Don't fail if there isn't a panel node available. While we're at it, use of_graph_get_endpoint_by_regs instead of of_graph_get_next_endpoint to make it more explicit that the LVDS output is at port 0. Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-09-15drm: Only use compat ioctl for addfb2 on X86/IA64Kristian H. Kristensen
Similar to struct drm_update_draw, struct drm_mode_fb_cmd2 has an unaligned 64 bit field (modifier). This get packed differently between 32 bit and 64 bit modes on architectures that can handle unaligned 64 bit access (X86 and IA64). Other architectures pack the structs the same and don't need the compat wrapper. Use the same condition for drm_mode_fb_cmd2 as we use for drm_update_draw. Note that only the modifier will be packed differently between compat and non-compat versions. Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org> [seanpaul added not at bottom of commit msg re: modifier] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1473801645-116011-1-git-send-email-hoegsberg@chromium.org
2016-09-15drm/qxl: squash lines for simple wrapper functionsMasahiro Yamada
Remove unneeded variables and assignments. Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1473863952-7658-5-git-send-email-yamada.masahiro@socionext.com
2016-09-15drm/bridge: analogix_dp: squash lines for simple wrapper functionsMasahiro Yamada
Remove unneeded variables and assignments. Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [seanpaul added analogix prefix to subject] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1473863952-7658-4-git-send-email-yamada.masahiro@socionext.com
2016-09-15drm/radeon: squash lines for simple wrapper functionsMasahiro Yamada
Remove unneeded variables and assignments. Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1473863952-7658-3-git-send-email-yamada.masahiro@socionext.com
2016-09-15drm/amdgpu: squash lines for simple wrapper functionsMasahiro Yamada
Remove unneeded variables and assignments. Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1473863952-7658-2-git-send-email-yamada.masahiro@socionext.com
2016-09-15drm/etnaviv: mark whole context as lost in recover workerLucas Stach
If we reset the GPU to get it back into a usable state we lose all context, not just the MMU one. Mark the whole context as lost to trigger a restore of the exec and MMU state. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: record correct cmdbuf IOVA in dumpLucas Stach
For cmdbufs the CPU IOVA was recorded instead of the GPU one. Fix this to make it consistent with other BOs and to make reading the dumps easier. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: space out IOVA layout for cmdbufs on MMUv2Lucas Stach
At least on the GC3000 the FE MMU is not properly flushing stale TLB entries. Make sure to map the cmdbufs with a big enough spacing in the IOVAs to not hit old/prefetched TLB entries when jumping to a newly mapped cmdbuf. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: fix up model and revision for GC2000+Lucas Stach
GC2000+ on the i.MX6QP is just a re-branded GC3000, lets call it by its real name to avoid confusion in other parts of the driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: implement IOMMUv2 translationLucas Stach
All other parts are now in place, so implement the actual translation step and hook it up, so the driver claims support for cores with the new MMU. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: handle MMU exception in IRQ handlerLucas Stach
Bit 30 of the interrupt status signals an MMU exception. Handle this condition properly and dump some useful registers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: add flushing logic for MMUv2Lucas Stach
Flushing works differently on MMUv2, in that it's only necessary to set a single bit in the control register to flush all translation units. A semaphore stall then makes sure that the flush has propagated properly. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: add function to construct MMUv2 init bufferLucas Stach
Both the safe/scratch address and the master TLB address are per pipe with the CPU mapped registers not properly propagating to the different translation units. The only way to correctly configure all translation units is to have a command stream snipped executed by the FE, before any other execution can start. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: map cmdbuf through MMU on version 2Lucas Stach
With MMUv2 all buffers need to be mapped through the MMU once it is enabled. Align the buffer size to 4K, as the MMU is only able to map page aligned buffers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: split out iova search and MMU reaping logicLucas Stach
With MMUv2 the command buffers need to be mapped through the MMU. Split out the iova search and MMU reaping logic so it can be reused for the cmdbuf mapping, where no GEM object is involved. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: split out FE startLucas Stach
Split out into a new externally visible function, as the IOMMUv2 code needs this functionality, too. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: split out wait for gpu idleLucas Stach
Split out into a new externally visible function, as the IOMMUv2 code needs this functionality, too. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: move gpu_va() to etnaviv mmuLucas Stach
The GPU virtual address for the command buffers differs depending on the IOMMU version. Move the calculation of the iova into etnaviv mmu, to enable proper dispatch. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: remove unused iommu_v2 headerLucas Stach
This has been there from the original merge, but has never been used. Get rid of it. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: move IOMMU domain allocation into etnaviv MMULucas Stach
The GPU code doesn't need to deal with the IOMMU directly, instead it can all be hidden behind the etnaviv mmu interface. Move the last remaining part into etnaviv mmu. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: indirect IOMMU restore through etnaviv MMULucas Stach
So we can call the v2 restore code once it is there. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: move linear window setup into etnaviv_iommuv1_restoreLucas Stach
It is only relevant for the V1 MMU, so we should not do this in the common code. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: rename etnaviv_iommu_domain_restore to etnaviv_iommuv1_restoreLucas Stach
This function has external visibility and only handles the Vivant IOMMU version 1. Rename to make this more clear and allow a clear separation of the different IOMMU versions. Also drop the domain parameter, as we can infer it from the GPU we are dealing with. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: only check if the cmdbuf is inside the linear window on MMUv1Lucas Stach
There is no linear window on MMUv2 and the FE can access the full 4GB address space either directly (as long as the MMU isn't configured) or through the MMU, once it is up. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: only try to use the linear window on MMUv1Lucas Stach
As the comment above the code states, the linear window is only available on MMUv1. Don't try to use it on MMUv2. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: fold various clock enable/disable functions into top onesLucas Stach
The driver doesn't ever enable individual clocks alone, so there is no need to scatter the clock enable/disable sequences through multiple functions. Fold them into the top one. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2016-09-15drm/etnaviv: remove unneeded variable initializationFabio Estevam
There is no need to initialize variable 'err' with 0 because it will be properly assigned later on. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2016-09-15drm/etnaviv: remove unneeded 'fail' labelFabio Estevam
In the etnaviv_gpu_platform_probe() error path the 'fail' label is used to just return the error code. This can be simplified by returning the error code immediately, so get rid of the unneeded 'fail' label. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2016-09-15drm/etnaviv: check for errors when enabling clocksFabio Estevam
clk_prepare_enable() may fail, so we should better check for its return value and propagate it in the case of failure. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2016-09-15drm: Add DP branch device info on debugfsMika Kahola
Read DisplayPort branch device info from through debugfs interface. v2: use drm_dp_helper routines to collect data v3: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v4: move DP branch device info to function 'intel_dp_branch_device_info()' v5: initial step to move debugging info from intel_dp. to drm_dp_helper.c (Daniel) v6: read hw and sw revision without using specific drm_dp_helper routines v7: indentation fixes (Jim Bride) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-12-git-send-email-mika.kahola@intel.com
2016-09-15drm/i915: Update bits per component for display infoMika Kahola
DisplayPort branch device may define max supported bits per component. Update display info based on this value if bpc is defined. v2: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v3: Fill bpc for connector's display info in separate drm_dp_helper function (Daniel) v4: remove updating bpc for display info as it may be overridden when parsing EDID. Instead, check bpc for DP branch device during compute_config v5: Indentation fixes (Jim Bride) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-11-git-send-email-mika.kahola@intel.com
2016-09-15drm/i915: Check pixel rate for DP to VGA dongleMika Kahola
Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville) v5: Use of intel_dp->downstream_ports to read out port capabilities. Code restructuring (Ville) v6: Move DP branch device check to drm_dp_helper.c (Daniel) v7: Cleanup as suggested by Ville Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-10-git-send-email-mika.kahola@intel.com
2016-09-15drm/i915: Read DP branch device SW revisionMika Kahola
SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register fields 0x50A and 0x50B. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) v3: remove dependency to drm_dp_helper but instead parse DPCD and print SW revision info to dmesg (Ville) v4: commit message fix (Jim Bride) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-9-git-send-email-mika.kahola@intel.com
2016-09-15drm/i915: Read DP branch device HW revisionMika Kahola
HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) v3: remove dependency to drm_dp_helper but instead parse DPCD and print HW revision info to dmesg (Ville) Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-8-git-send-email-mika.kahola@intel.com
2016-09-15drm/i915: Cleanup DisplayPort AUX channel initializationMika Kahola
Let's remove reference to "struct intel_connector *connector" in intel_dp_aux_init() function as it is no longer required. Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-7-git-send-email-mika.kahola@intel.com
2016-09-15drm: Read DP branch device idMika Kahola
Read DisplayPort branch device id string. Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-6-git-send-email-mika.kahola@intel.com
2016-09-15drm: Helper to read max bits per componentMika Kahola
Helper routine to read out maximum supported bits per component for DisplayPort legay converters. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case (Ville) Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-5-git-send-email-mika.kahola@intel.com
2016-09-15drm: Helper to read max clock rateMika Kahola
Helper routine to read out maximum supported pixel rate for DisplayPort legay VGA converter or TMDS clock rate for other digital legacy converters. The helper returns clock rate in kHz. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case (Ville) Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-4-git-send-email-mika.kahola@intel.com
2016-09-15drm/i915: Add ddb size field to device info structureDeepak M
Adding the ddb size into the devide info will avoid platform checks while computing wm. v2: Added comment and WARN_ON if ddb size is zero.(Jani) v3: Added WARN_ON at the right place.(Jani) Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Deepak M <m.deepak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473931870-7724-1-git-send-email-m.deepak@intel.com
2016-09-15drm/i915/guc: general tidying up (submission)Dave Gordon
Renaming to more consistent scheme, and updating comments, mostly about i915_guc_wq_reserve(), aka i915_guc_wq_check_space(). Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473711577-11454-4-git-send-email-david.s.gordon@intel.com Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-15drm/i915/guc: general tidying up (loader)Dave Gordon
Renaming to more consistent scheme, delete unused definitions Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473711577-11454-3-git-send-email-david.s.gordon@intel.com Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-15drm/i915: clarify PMINTRMSK/pm_intr_keep usageDave Gordon
No functional changes; just renaming a bit, tweaking a datatype, prettifying layout, and adding comments, in particular in the GuC setup code that touches this data. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473711577-11454-2-git-send-email-david.s.gordon@intel.com Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-15drm/i915: Only expand COND once in wait_for()Dave Gordon
Commentary from Chris Wilson's original version: > I was looking at some wait_for() timeouts on a slow system, with lots of > debug enabled (KASAN, lockdep, mmio_debug). Thinking that we were > mishandling the timeout, I tried to ensure that we loop at least once > after first testing COND. However, the double test of COND either side > of the timeout check makes that unlikely. But we can do an equivalent > loop, that keeps the COND check after testing for timeout (required so > that we are not preempted between testing COND and then testing for a > timeout) without expanding COND twice. > > The advantage of only expanding COND once is a dramatic reduction in > code size: > > text data bss dec hex > 1308733 5184 1152 1315069 1410fd before > 1305341 5184 1152 1311677 1403bd after but it turned out that due to a missing iniitialiser, gcc had "gone wild trimming undefined code" :( This version acheives a rather more modest (but still worthwhile) gain of ~550 bytes. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Original-idea-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473855033-26980-1-git-send-email-david.s.gordon@intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-14drm/amdgpu: use explicit limit for VRAM<->GTT movesChristian König
Use an explicit limit when moving things around to force address space allocation. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-14drm/amdgpu: use explicit GTT limit for evictionsChristian König
This way the address space gets allocated immediately. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-14drm/amdgpu: unbind GTT only when it is boundChristian König
Doesn't make much sense to clear the GTT when it was never filled. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-14drm/amdgpu: add AMDGPU_BO_INVALID_OFFSETChristian König
An invalid offset to be used by custom VRAM/GGT manager when we don't have an offset for an BO. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-14drm/amdgpu: validate size and offset of user fence BOChristian König
We need to validate the offset to make sure that we don't write after the BO. Additional to that a page should be enough and can make address space handling much easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-14drm/ttm: rework handling of private mem typesChristian König
Instead of keeping a bunch of potentially unused flags, just define the start for private memory types and remove the rest. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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