Age | Commit message (Collapse) | Author |
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Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GM200.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with TU104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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No real surprised here so far.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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RTX2070 appears to have 3 copies of the engine.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Various different bits and pieces vs GV100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GV100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP102.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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New registers.
Currently uncertain how exactly to mask fault buffer interrupts. This will
likely be corrected at around the same time as the new MC interrupt stuff
has been properly figured out and implemented.
For the moment, it shouldn't matter too much.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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New registers.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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New flush method.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP102.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GV100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with NV50.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GK20A.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GF100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Things are a bit different here on Turing, and will require further changes
yet once I've investigated them more thoroughly.
For now though, the existing GP100 code is compatible enough with one small
hack to forward on fault buffer interrupts.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GM107.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GM200.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GM200.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GK104.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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The GPU executes DEVINIT itself now, which makes our lives a bit easier.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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No real surprises here so far.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Turing GPUs can have more than one.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Depending on the kernel configuration, early ARM architecture setup code
may have attached the GPU to a DMA/IOMMU mapping that transparently uses
the IOMMU to back the DMA API. Tegra requires special handling for IOMMU
backed buffers (a special bit in the GPU's MMU page tables indicates the
memory path to take: via the SMMU or directly to the memory controller).
Transparently backing DMA memory with an IOMMU prevents Nouveau from
properly handling such memory accesses and causes memory access faults.
As a side-note: buffers other than those allocated in instance memory
don't need to be physically contiguous from the GPU's perspective since
the GPU can map them into contiguous buffers using its own MMU. Mapping
these buffers through the IOMMU is unnecessary and will even lead to
performance degradation because of the additional translation. One
exception to this are compressible buffers which need large pages. In
order to enable these large pages, multiple small pages will have to be
combined into one large (I/O virtually contiguous) mapping via the
IOMMU. However, that is a topic outside the scope of this fix and isn't
currently supported. An implementation will want to explicitly create
these large pages in the Nouveau driver, so detaching from a DMA/IOMMU
mapping would still be required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP102.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GM107.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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VEID support hacked in here, as it's the most convenient place for now.
Will be refined once it's better understood.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP102.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Can't imagine this will be any different.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GK20A.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GF100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Appears to be compatible with GP100.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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