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path: root/drivers/gpu/drm/nouveau/nvkm/engine/device
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2020-01-15drm/nouveau/nvdec/gm107: rename from gp102 implementationBen Skeggs
NVDEC is available from GM107, and we currently only have a stub implementation anyway, let's make it explicit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/sec2/gp108: split from gp102 implementationBen Skeggs
ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP108/GV100 FWs differ from the other GP10x boards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/gr/gp108: split from gp107Ben Skeggs
ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP107/GP108 FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/pmu/gp10b: split from gm20b implementationBen Skeggs
ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GM20B/GP10B FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/acr: add stub implementation for all GPUs currently supported by ↵Ben Skeggs
SECBOOT PMU, SEC2 and GR will be modified to register their falcons with ACR before the main commit switching everything over. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/core: define ACR subdevBen Skeggs
This will replace the current SECBOOT subdev for handling firmware on secure falcons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/ce/gp10b: Use correct copy engineThierry Reding
gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine class because on gp10b the PASCAL_DMA_COPY_B class is not supported. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/ltc/gp10b: Add custom L2 cache implementationThierry Reding
There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/tegra: Set clock rate if not setThierry Reding
If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/tegra: Avoid pulsing reset twiceThierry Reding
When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power-ungate procedure can cause the GPU to go into a bad state where the memory interface can no longer access system memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/fault: Add support for GP10BThierry Reding
There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault buffer. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau: fix bogus GPL-2 license headerBen Skeggs
The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files were simply missing the boiler plate and got caught up in the global update. Fixes: 96ac6d4351004 (treewide: Add SPDX license identifier - Kbuild) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau: fix bogus GPL-2 license headerIlia Mirkin
The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files (primarily header files) were simply missing the boiler plate and got caught up in the global update. Fixes: b24413180f5 (License cleanup: add SPDX GPL-2.0 license identifier to files with no license) Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Emil Velikov <emil.l.velikov@gmail.com> Acked-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau/core: recognise TU116 chipsetBen Skeggs
Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing graphics/compute bring-up. Each subsystem was compared with traces, along with various tests to check that things generally work as they should, and appears compatible enough with the current TU117 code to enable support. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau/mcp89/mmu: Use mcp77_mmu_new instead of g84_mmu_new on MCP89.Timo Wiren
Fix a crash or broken depth testing in all OpenGL applications that use the depth buffer on MCP89 (GeForce 320M) seen on a MacBook Pro Late 2010. The bug is tracked in https://bugs.freedesktop.org/show_bug.cgi?id=108500 Signed-off-by: Timo Wiren <timo.wiren@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-05-30treewide: Add SPDX license identifier - KbuildGreg Kroah-Hartman
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0 Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-14drm/nouveau/core: initial support for boards with TU117 chipsetBen Skeggs
Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing graphics/compute bring-up. Each subsystem was compared with traces, along with various tests to check that things generally work as they should, and appears compatible enough with the current TU106 code to enable support. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-05-14drm/nouveau/core: allow detected chipset to be overriddenBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/fault/gp100: expose MaxwellFaultBufferABen Skeggs
This nvclass exposes the replayable fault buffer, which will be used by SVM to manage GPU page faults. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/sec2/tu102-: instantiate SEC2 falconBen Skeggs
Required for ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/nvdec/tu102-: instantiate NVDEC0 falconBen Skeggs
Required to run VPR scrubber binary as part of secboot. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gsp/gv100-: instantiate GSP falconBen Skeggs
We need this for Turing ACR, but it's present from Volta onwards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/core: define GSP subdevBen Skeggs
Exact meaning of the acronym is unknown, but we need this for Turing ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/ce/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/fifo/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/disp/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/fault/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/bar/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/mmu/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/mc/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/devinit/tu102: rename implementation from tu104Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/volt/gf117: fix speedo readout registerIlia Mirkin
GF117 appears to use the same register as GK104 (but still with the general Fermi readout mechanism). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-01-18drm/nouveau/core: recognise TU102Ben Skeggs
Would usually do this split-out, verifying each component indivitually, but this has been squashed together to be more palatable for merging in 5.0-rc. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/ce/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/disp/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/dma/tu106: initial supportBen Skeggs
Appears to be compatible with GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/therm/tu106: initial supportBen Skeggs
Appears to be compatible with GP100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/pmu/tu106: initial supportBen Skeggs
Appears to be compatible with GP102. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fault/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bar/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mmu/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/ltc/tu106: initial supportBen Skeggs
Appears to be compatible with GP102. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fb/tu106: initial supportBen Skeggs
Appears to be compatible with GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/imem/tu106: initial supportBen Skeggs
Appears to be compatible with NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/tmr/tu106: initial supportBen Skeggs
Appears to be compatible with GK20A. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bus/tu106: initial supportBen Skeggs
Appears to be compatible with GF100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mc/tu106: initial supportBen Skeggs
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fuse/tu106: initial supportBen Skeggs
Appears to be compatible with GM107. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/i2c/tu106: initial supportBen Skeggs
Appears to be compatible with GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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