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path: root/drivers/gpu/drm/nouveau/include
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2016-03-14drm/nouveau/subdev/iccsense: add new subdev for power sensorsMartin Peres
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/secboot/gm20b: add secure boot supportAlexandre Courbot
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/secboot/gm200: add secure-boot supportAlexandre Courbot
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add support for secure bootAlexandre Courbot
On GM200 and later GPUs, firmware for some essential falcons (notably GR ones) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to be able to access privileged registers, in a process known as Secure Boot. Secure Boot requires building a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure falcon running a signed loader firmware that copies the blob into a write-protected region, checks that the signatures are valid, and finally loads the verified firmware into the managed falcons and switches them to privileged mode. This patch adds infrastructure code to support this process on chips that require it. v2: - The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. - The falcon reset procedure expecting a falcon in an initialized state, which was accidentally provided by the PMU subdev. Make sure that secboot can manage the falcon on its own. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add gpuobj memcpy helper functionsAlexandre Courbot
Add memcpy functions to copy a buffer to a gpuobj and vice-versa. This will be used by the secure boot code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: s/gm204/gm200/Ben Skeggs
Most of the per-chipset differences will go away when we fully switch to using the register lists provided by the firmware files, which will leave all the remaining code "belonging" to GM200. This is a preemptive rename from GM204 to GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau: s/gm204/gm200/ in a number of placesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add firmware handling functionsAlexandre Courbot
Add two functions nvkm_firmware_get() and nvkm_firmware_put() to load a firmware file and free its resources, respectively. Since firmware files are becoming a necessity for new GPUs, and their location has been standardized to nvidia/chip/, this will prevent duplicate and error-prone name-generation code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/perf: add fields for pci speed and width and use it for the pstatesKarol Herbst
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11drm/nouveau/bios/perf: parse the pci speed from the bios for tesla and newer ↵Karol Herbst
cards Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11drm/nouveau/pci: implement generic code for pcie speed changeKarol Herbst
v2: rename and group functions v4: change copyright information move printing of pcie speeds into oneinit, rename all pcie functions to nvkm_pcie_* don't try to raise the pcie version when no higher one is supported v5: revert Copyright changes and rename nvkm_pcie_raise_version to nvkm_pcie_set_version v6: remove some useless pci_is_pcie checks and rework messages Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11drm/nouveau/pci: add gk104 variantKarol Herbst
v2: change email used in header v4: change Copyright information v5: revert Copyright changes Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11drm/nouveau/pci: add gf106 variantKarol Herbst
v2: change email used in header v4: change Copyright information v5: revert Copyright changes Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11drm/nouveau/nouveau/perfmon: add interface files for current core voltageKarol Herbst
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/clk: remove references to "daemon"Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/ltc/gm204: split implementation from gm107Ben Skeggs
Differences from GM10x: - GM20x LTC count detection differs from GM10x - GM20x init doesn't require large page size setting Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/ibus/gm204: split implementation from gk104Ben Skeggs
GM20x doesn't require the priv ring timeout bumps that GK/GM10x have. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: modify nvif_unvers/nvif_unpack macros to be more obviousBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out client interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out device interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out ctxdma interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out perfmon interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out device control interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out fifo interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out display interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out nvsw interface definitonsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: split out fermi interface definitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11drm/nouveau/nvif: move internal class identifiers to class.hBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-12-09drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by defaultBen Skeggs
NVIDIA have indicated that the workaround is required on all GK10[467] boards that have the PGOB fuse set. I've left the commandline option in place for now, as paranoia. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/instmem: protect instobj list with a spinlockBen Skeggs
No locking is required for the traversal of this list, as it only happens during suspend/resume where nothing else can be executing. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet
Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/bios/rammap: Identify DLLoff for >= GF100Roy Spliet
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci: Handle 5-bit and 8-bit tag fieldPierre Moreau
If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: remove unused functionSudip Mukherjee
coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs
Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/g94: split implementation from nv40Ben Skeggs
An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/g84: split implementation from nv50Ben Skeggs
An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset
Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/volt/gk104: add support for pwm and gpio modesMartin Peres
Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/bios/volt: add support for pwm-based volt managementMartin Peres
Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/platform: allow to specify the IOMMU bitAlexandre Courbot
Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ltc/gf100: add flush/invalidate functionsAlexandre Courbot
Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ltc: add hooks for invalidate and flushAlexandre Courbot
These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/timer: re-introduce nvkm_wait_xsec macrosAlexandre Courbot
Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/tegra: merge platform setup from nouveau drmBen Skeggs
The copyright header in nvkm/engine/device/platform.c has been replaced with the NVIDIA one from drm/nouveau_platform.c, as most of the actual code is now theirs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pci: merge agp handling from nouveau drmBen Skeggs
This commit reinstates the pre-DEVINIT AGP fiddling that was broken in an earlier commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: remove pci/platform_device from common structBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: import pciid list and integrate quirks with itBen Skeggs
PCI IDs taken from the NVIDIA binary driver, with permission. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: cleaner abstraction for device resource functionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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