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path: root/drivers/gpu/drm/msm/disp
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2023-05-22drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASKKonrad Dybcio
DPU5 and newer targets enable this unconditionally. Move it from the SC7280 mask to the SC7180 one. Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/538159/ Link: https://lore.kernel.org/r/20230508-topic-hctl_en-v2-1-e7bea9f1f5dd@linaro.org [DB: removed BIT(DPU_INTF_DATA_COMPRESS), which is not yet merged] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: access CSC/CSC10 registers directlyDmitry Baryshkov
Stop using _sspp_subblk_offset() to get offset of the csc_blk. Inline this function and use ctx->cap->sblk->csc_blk.base directly. As this was the last user, drop _sspp_subblk_offset() too. Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534747/ Link: https://lore.kernel.org/r/20230429012353.2569481-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: access QSEED registers directlyDmitry Baryshkov
Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline this function and use ctx->cap->sblk->scaler_blk.base directly. Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534746/ Link: https://lore.kernel.org/r/20230429012353.2569481-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: drop SSPP's SRC subblockDmitry Baryshkov
The src_blk declares a lame copy of main SSPP register space. It's offset is always 0. It's length has been fixed to 0x150, while SSPP's length is now correct. Drop the src_blk and access SSPP registers without additional subblock lookup. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534745/ Link: https://lore.kernel.org/r/20230429012353.2569481-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Remove intr_rdptr from DPU >= 5.0.0 pingpong configMarijn Suijten
Now that newer DPU platforms use a readpointer-done interrupt on the INTF block, stop providing the unused interrupt on the PINGPONG block. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534238/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-22-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Implement tearcheck support on INTF blockMarijn Suijten
Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the PINGPONG block and into the INTF. Implement the necessary callbacks in the INTF block, and use these callbacks together with the INTF_TEAR interrupts. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534234/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-21-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Merge setup_- and enable_tearcheck pingpong callbacksMarijn Suijten
These functions are always called consecutively and are best bundled together for simplicity, especially when the same structure of callbacks will be replicated later on the interface block for INTF TE support. The enable_tearcheck(false) case is now replaced with a more obvious disable_tearcheck(), encapsulating the original register write with 0. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534217/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-20-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF blockMarijn Suijten
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of the PINGPONG block and into the INTF block. The new interrupts are described in dpu_hw_interrupts.c, now wire them up in individual SoC catalog files by setting the intr_tear_rd_ptr to the IRQ index spcified in the offset table and enabling this set of DPU interrupts via the mdss_irqs bitmask. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534236/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-19-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Describe TEAR interrupt registers for DSI interfacesMarijn Suijten
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of the PINGPONG block and into the INTF block. Wire up the IRQ register masks in the interrupt table for enabling, reading and clearing them. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534244/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-18-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macroMarijn Suijten
As the INTF block is going to attain more interrupts that don't share the same MDP_SSPP_TOP0_INTR register, factor out the _reg argument for the caller to construct the right interrupt index (register and bit index) to not make the interrupt bit arguments depend on one of multiple interrupt register indices. This brings us more in line with how PP_BLK specifies its interrupts and allows for better wrapping in the arrays. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534222/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-17-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Move dpu_hw_{tear_check, pp_vsync_info} to dpu_hw_mdss.hKonrad Dybcio
Now that newer SoCs since DPU 5.0.0 manage tearcheck in the INTF instead of PINGPONG block, move the struct definition to a common file. Also, bring in documentation from msm-4.19 techpack while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [Marijn: Also move dpu_hw_pp_vsync_info] Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534232/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-16-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Disable MDP vsync source selection on DPU 5.0.0 and aboveMarijn Suijten
Since hardware revision 5.0.0 the TE configuration moved out of the PINGPONG block into the INTF block, including vsync source selection that was previously part of MDP top. Writing to the MDP_VSYNC_SEL register has no effect anymore and is omitted downstream via the DPU/SDE_MDP_VSYNC_SEL feature flag. This flag is only added to INTF blocks used by hardware prior to 5.0.0. The code that writes to these registers in the INTF block will follow in subsequent patches. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534220/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-15-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Disable pingpong TE on DPU 5.0.0 and aboveMarijn Suijten
Since hardware revision 5.0.0 the TE configuration moved out of the PINGPONG block into the INTF block. Writing these registers has no effect, and is omitted downstream via the DPU/SDE_PINGPONG_TE feature flag. This flag is only added to PINGPONG blocks used by hardware prior to 5.0.0. The existing PP_BLK_TE macro has been removed in favour of directly passing this feature flag, which has thus far been the only difference with PP_BLK. PP_BLK_DITHER has been left in place as its embedded feature flag already excludes this DPU_PINGPONG_TE bit and differs by setting the block length to zero, as it only contains a DITHER subblock. The code that writes to these registers in the INTF block will follow in subsequent patches. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534240/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-14-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Move autorefresh disable from CMD encoder to pingpongMarijn Suijten
This autorefresh disable logic in the physical command-mode encoder consumes three callbacks to the pingpong block, and will explode in unnecessary complexity when the same callbacks need to be called on the interface block instead to accommodate INTF TE support. To clean this up, move the logic into the pingpong block under a disable_autorefresh callback, replacing the aforementioned three get_autorefresh, setup_autorefresh and get_vsync_info callbacks. The same logic will have to be replicated to the interface block when it receives INTF TE support, but it is less complex than constantly switching on a "has_intf_te" boolean to choose a callback. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534230/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-13-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Drop unused poll_timeout_wr_ptr PINGPONG callbackMarijn Suijten
This callback was migrated from downstream when DPU1 was first introduced to mainline, but never used by any component. Drop it to save some lines and unnecessary confusion. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534215/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-12-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Take INTF index as parameter in interrupt register definesMarijn Suijten
Instead of hardcoding many register defines for every INTF and AD4 index with a fixed stride, turn the defines into singular chunks of math that compute the address using the base and this fixed stride multiplied by the index given as argument to the definitions. MDP_SSPP_TOP0_OFF is dropped as that constant is zero anyway, and all register offsets related to it live in dpu_hwio.h. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534221/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-11-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Sort INTF registers numericallyMarijn Suijten
A bunch of registers were appended at the end in e.g. commit 91143873a05d ("drm/msm/dpu: Add MISR register support for interface") rather than being inserted in a place that maintains numerical sorting: restore said numerical sorting. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534213/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-10-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Remove extraneous register define indentationMarijn Suijten
A bunch of registers are indented with two extra spaces, looking as if these are values corresponding to the previous register which is not the case, rather these are simply also register offsets and should only have a single space separating them and the #define keyword. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534218/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-9-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Use V4.0 PCC DSPP sub-block in SC7[12]80Marijn Suijten
According to various downstream sources the PCC sub-block inside DSPP is version 4.0 since DPU 4.0 and higher, including SC7[12]80 at DPU version 6.2 and 7.2 respectively. After correcting the version this struct becomes identical to sm8150_dspp_sblk which is used all across the catalog: replace uses of sc7180_dspp_sblk with that and remove the struct definition for sc7180_dspp_sblk entirely. Fixes: 4259ff7ae509e ("drm/msm/dpu: add support for pcc color block in dpu driver") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/537899/ Link: https://lore.kernel.org/r/20230518-dpu-sc7180-pcc-version-v1-1-ec9ca4949e3e@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: add writeback support for sc7280Abhinav Kumar
Add writeback support for sc7280. This was validated with kms_writeback test case in IGT. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/535244/ Link: https://lore.kernel.org/r/20230503223905.24754-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: drop unused SSPP sub-block informationDmitry Baryshkov
The driver doesn't support hsic/memcolor and pcc SSPP subblocks. Drop corresponding definitions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534766/ Link: https://lore.kernel.org/r/20230429212512.2947245-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: drop DSPP_MSM8998_MASK from hw catalogAbhinav Kumar
Since GC and IGC masks have now been dropped, DSPP_MSM8998_MASK is the same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more than DSPP_MSM8998_MASK, lets drop the latter. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534726/ Link: https://lore.kernel.org/r/20230428223646.23595-4-quic_abhinavk@quicinc.com [DB: fixed typo in commit message] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: remove GC and IGC related code from dpu catalogAbhinav Kumar
Gamma Correction (GC) and Inverse Gamma Correction(IGC) is currently unused. In addition dpu_dspp_sub_blks didn't even have an igc member describing the block. Drop related code from the dpu hardware catalog otherwise this becomes a burden to carry across chipsets in the catalog. changes in v3: - drop IGC related code from dpu_hw_catalog too - update commit text accordingly Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534725/ Link: https://lore.kernel.org/r/20230428223646.23595-3-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: remove DPU_DSPP_IGC handling in dspp flushAbhinav Kumar
Inverse gamma correction blocks (IGC) are not used today so lets remove the usage of DPU_DSPP_IGC in the DSPP flush to make it easier to remove IGC from the catalog. We can add this back when IGC is properly supported in DPU with one of the standard DRM properties. changes in v3: - minor change dspp -> DSPP in commit text Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534724/ Link: https://lore.kernel.org/r/20230428223646.23595-2-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: remove DPU_DSPP_GC handling in dspp flushAbhinav Kumar
Gamma correction blocks (GC) are not used today so lets remove the usage of DPU_DSPP_GC in the dspp flush to make it easier to remove GC from the catalog. We can add this back when GC is properly supported in DPU with one of the standard DRM properties. changes in v3: - drop the link tag which was auto added before Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534723/ Link: https://lore.kernel.org/r/20230428223646.23595-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Pass catalog pointers in RM to replace for-loop ID lookupsMarijn Suijten
The Resource Manager already iterates over all available blocks from the catalog, only to pass their ID to a dpu_hw_xxx_init() function which uses an _xxx_offset() helper to search for and find the exact same catalog pointer again to initialize the block with, fallible error handling and all. Instead, pass const pointers to the catalog entries directly to these _init functions and drop the for loops entirely, saving on both readability complexity and unnecessary cycles at boot. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/533861/ Link: https://lore.kernel.org/r/20230418-dpu-drop-useless-for-lookup-v3-3-e8d869eea455@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: Drop unused members from HW structsMarijn Suijten
Some of these members were initialized while never read, while others were not even assigned any pointer value at all. Drop them to save some space, and above all confusion when looking at or accidentally dereferencing these members. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/533862/ Link: https://lore.kernel.org/r/20230418-dpu-drop-useless-for-lookup-v3-2-e8d869eea455@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: stop mapping the regdma regionDmitry Baryshkov
Stop mapping the regdma region. The driver does not support regdma. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/533150/ Link: https://lore.kernel.org/r/20230420222558.1208887-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: drop the regdma configurationDmitry Baryshkov
The regdma is currently not used by the current driver. We have no way to practically verify that the regdma is described correctly. Drop it now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/533148/ Link: https://lore.kernel.org/r/20230420222558.1208887-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: set max cursor width to 512x512Arnaud Vrac
Override the default max cursor size reported to userspace of 64x64. MSM8998 hw cursor planes support 512x512 size, and other chips use DMA SSPPs. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/532903/ Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-9-d1bac46db075@freebox.fr Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: fix cursor block register bit offset in msm8998 hw catalogArnaud Vrac
This matches the value for both fbdev and sde implementations in the downstream msm-4.4 repository. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/532899/ Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-8-d1bac46db075@freebox.fr Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: use hsync/vsync polarity set by the encoderArnaud Vrac
Do not override the hsync/vsync polarity passed by the encoder when setting up intf timings. The same logic was used in both the encoder and intf code to set the DP and DSI polarities, so those interfaces are not impacted. However for HDMI, the polarities were overriden to static values based on the vertical resolution, instead of using the actual mode polarities. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/532901/ Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-3-d1bac46db075@freebox.fr Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-22drm/msm/dpu: add HDMI output supportDmitry Baryshkov
MSM8998 and the older Qualcomm platforms support HDMI outputs. Now as DPU encoder is ready, add support for using INTF_HDMI. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Arnaud Vrac <rawoul@gmail.com> Tested-by: Arnaud Vrac <rawoul@gmail.com> # on msm8998 Patchwork: https://patchwork.freedesktop.org/patch/532371/ Link: https://lore.kernel.org/r/20230415171926.85774-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-19drm/msm/dpu: simplify intf allocation codeDmitry Baryshkov
Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess, which intf type we mean, pass INTF_DSI/INTF_DP directly. This is required to support HDMI output in DPU, as both DP and HDMI encoders are DRM_MODE_ENCODER_TMDS. Thus dpu_encoder code can not make a difference between HDMI and DP outputs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Arnaud Vrac <rawoul@gmail.com> Tested-by: Arnaud Vrac <rawoul@gmail.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/532370/ Link: https://lore.kernel.org/r/20230415171926.85774-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-19drm/msm/dpu: use CTL_SC7280_MASK for sm8450's ctl_0Dmitry Baryshkov
On sm8450 platform the CTL_0 doesn't differ from the rest of CTL blocks, so switch it to CTL_SC7280_MASK too. Some background: original commit 100d7ef6995d ("drm/msm/dpu: add support for SM8450") had all (relevant at that time) bit spelled individually. Then commit 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog"), despite being a mismerge, correctly changed all other CTL entries to use CTL_SC7280_MASK, except CTL_0. While the current BLOCK_SOC_MASK style is not ideal (and while we are working on a better scheme), let's follow its usage as a least minimal surprise. For example, sc8280xp, a close associate of sm8450, also uses CTL_SC7280_MASK. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/531493/ Link: https://lore.kernel.org/r/20230408002750.2722304-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-19drm/msm/dpu: enable DSPP and DSC on sc8180xDmitry Baryshkov
Enable DSPP and DSC hardware blocks on sc8180x platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/531490/ Link: https://lore.kernel.org/r/20230408002750.2722304-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-19drm/msm/dpu: enable DSPP_2/3 for LM_2/3 on sm8450Dmitry Baryshkov
Mark DSPP_2 and DSPP_3 as used for LM_2 and LM_3 Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/531491/ Link: https://lore.kernel.org/r/20230408002750.2722304-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-05-19drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xpDmitry Baryshkov
Theoretically, since sm8150 we should be using a single CTL for the split panel case, but since we do not support it for now, fallback to DPU_CTL_SPLIT_DISPLAY. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/531489/ Link: https://lore.kernel.org/r/20230408002750.2722304-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-04-26drm/msm/dpu: Remove duplicate register defines from INTFMarijn Suijten
The INTF_FRAME_LINE_COUNT_EN, INTF_FRAME_COUNT and INTF_LINE_COUNT registers are already defined higher up, in the right place when sorted numerically. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534231/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-8-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Set PINGPONG block length to zero for DPU >= 7.0.0Marijn Suijten
Despite downstream DTS stating otherwise, the PINGPONG block has no registers starting with DPU revision 7.0.0. TEAR registers are gone since DPU 5.0.0 after being moved to the INTF block, and DSC registers are gone since 7.0.0, leaving only the dither sub-block. A future patch, part of the DSC 1.2 series, should disable DSC functions on the PINGPONG block for all DPU >= 7.0.0 hardware. Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534206/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-7-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Use V2 DITHER PINGPONG sub-block in SM8[34]50/SC8280XPMarijn Suijten
According to downstream sources this DITHER sub-block sits at an offset of 0xe0 with version 0x20000. Lets fix this by using sc7280_pp_sblk instead of sdm845_pp_sblk. Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534208/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-6-27ce1a5ab5c6@somainline.org [quic_abhinavk@quicinc.com: minor fix in the commit message] Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typoMarijn Suijten
SM8550 exclusively has a DITHER sub-block inside the PINGPONG block and no other registers, hence the DITHER name of the macro and a corresponding PINGPONG block length of zero. However, the PP_BLK_ macro name was typo'd to DIPHER rather than DITHER. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534214/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-5-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Reindent REV_7xxx interrupt masks with tabsMarijn Suijten
Use tabs for consistency with the other interrupt register definitions, rather than spaces. Fixes: ed6154a136e4 ("drm/msm/disp/dpu1: add intf offsets for SC7280 target") Fixes: 89688e2119b2 ("drm/msm/dpu: Add more of the INTF interrupt regions") Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534212/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-4-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio headerMarijn Suijten
These offsets do not fall under the MDP TOP block and do not fit the comment right above. Move them to dpu_hw_interrupts.c next to the repsective MDP_INTF_x_OFF interrupt block offsets. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534203/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-3-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Remove TE2 block and feature from DPU >= 5.0.0 hardwareMarijn Suijten
No hardware beyond kona (sm8250, DPU 6.0.0) defines the TE2 PINGPONG sub-block offset downstream, and according to insiders no DPU >= 5.0.0 hardware has support for it either. Especially since neither downstream nor upstream utilize these registers in any way, remove the erroneous specification from SM8150, SC8180X, SM8250, SC7180, SM8350, SC8280XP and SM8450 to prevent confusion. Note that downstream enables the PPSPLIT (split-FIFO) topology (single LM for 2 PP and 2 INTF) based on the presence of a TE2 block. Fixes: 386fced3f76f ("drm/msm/dpu: add SM8150 to hw catalog") Fixes: 7bdc0c4b8126 ("msm:disp:dpu1: add support for display for SC7180 target") Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534210/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Remove unused INTF0 interrupt mask from SM6115/QCM2290Marijn Suijten
Neither of these SoCs has INTF0, they only have a DSI interface on index 1. Stop enabling an interrupt that can't fire. Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534204/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: tweak lm pairings in msm8998 hw catalogArnaud Vrac
Change lm blocks pairs so that lm blocks with the same features are paired together: LM_0 and LM_1 with PP and DSPP LM_2 and LM_5 with PP LM_3 and LM_4 This matches the sdm845 configuration and allows using pp or dspp when 2 lm blocks are needed in the topology. In the previous config the reservation code could never find an lm pair without a matching feature set. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/532905/ Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-10-d1bac46db075@freebox.fr Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: tweak msm8998 hw catalog valuesArnaud Vrac
Match the values found in the downstream msm-4.4 kernel sde driver. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/532900/ Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-1-d1bac46db075@freebox.fr Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-26drm/msm/dpu: Assign missing writeback log_maskMarijn Suijten
The WB debug log mask ended up never being assigned, leading to writes to this block to never be logged even if the mask is enabled in dpu_hw_util_log_mask via debugfs. Fixes: 84a33d0fd921 ("drm/msm/dpu: add dpu_hw_wb abstraction for writeback blocks") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/533860/ Link: https://lore.kernel.org/r/20230418-dpu-drop-useless-for-lookup-v3-1-e8d869eea455@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2023-04-07drm/msm/dpu: drop unused macros from hw catalogDmitry Baryshkov
Drop the version comparison macros from dpu_hw_catalog.h, they are unused. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530889/ Link: https://lore.kernel.org/r/20230404130622.509628-43-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 10:23:00 +0000