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path: root/drivers/gpu/drm/i915/intel_display.c
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2019-03-26drm/i915: add uncore flags for unclaimed mmioDaniele Ceraolo Spurio
Save the HW capabilities to avoid having to jump back to dev_priv every time. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-4-daniele.ceraolospurio@intel.com
2019-03-22drm/i915/ehl: EHL outputs are different from ICLBob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's plus DSI. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190322175847.25707-4-rodrigo.vivi@intel.com
2019-03-21drm/fourcc: Fix conflicting Y41x definitionsMaarten Lankhorst
There has unfortunately been a conflict with the following 3 commits: commit e9961ab95af81b8d29054361cd5f0c575102cf87 Author: Ayan Kumar Halder <ayan.halder@arm.com> Date: Fri Nov 9 17:21:12 2018 +0000 drm: Added a new format DRM_FORMAT_XVYU2101010 commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3 Author: Brian Starkey <brian.starkey@arm.com> Date: Fri Oct 5 10:27:00 2018 +0100 drm/fourcc: Add AFBC yuv fourccs for Mali and commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b Author: Swati Sharma <swati2.sharma@intel.com> Date: Mon Mar 4 17:26:33 2019 +0530 drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc Unfortunately gcc didn't warn about the redefinitions, because the double defines were the set to same value, and gcc apparently no longer warns about that. Fix this by using new XYVU for i915, without alpha, and making the Y41x definitions match msdn, with alpha. Fortunately we caught it early, and the conflict hasn't even landed in drm-next yet. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Ayan Kumar Halder <ayan.halder@arm.com> Cc: malidp@foss.arm.com Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Sean Paul <sean@poorly.run> Cc: Dave Airlie <airlied@linux.ie> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190319121702.6814-1-maarten.lankhorst@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com> #irc Acked-by: Sean Paul <sean@poorly.run> Reviewed-by: Ayan Kumar halder <ayan.halder@arm.com>
2019-03-20drm/i915: use intel_uncore for all forcewake get/putDaniele Ceraolo Spurio
Now that the internal code all works on intel_uncore, flip the external-facing interface. v2: fix GVT. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-4-daniele.ceraolospurio@intel.com
2019-03-20drm/i915: Introduce i9xx_has_pps()Ville Syrjälä
Add a small helper to determine if we have the panel power sequencer or not. We'll make PNV an exceptional case so that we can unset .is_mobile for the desktop variant. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318165633.28924-3-ville.syrjala@linux.intel.com Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2019-03-20drm/i915: Introduce i9xx_has_pfit()Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit(). Also make PNV an exceptional case so that we can unset .is_mobile for the desktop variant. v2: s/gen4/gen>=4/ (Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190319142329.22881-1-ville.syrjala@linux.intel.com Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2019-03-19drm/i915: Pass dev_priv to intel_is_dual_link_lvds()Ville Syrjälä
Make things look a bit nicer by passing dev_priv to intel_is_dual_link_lvds(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318202653.15217-3-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-03-19drm/i915: Add some missing curly bracesVille Syrjälä
Sprinkle some curly braces in accordance with the coding style. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318202653.15217-1-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-03-19drm/i915: Pass crtc_state down to bxt dpll funcsVille Syrjälä
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-5-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll()Ville Syrjälä
Passing both crtc and its state is redundant. Pass just the state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-2-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-18Merge tag 'topic/hdr-formats-2019-03-13' of ↵Joonas Lahtinen
git://anongit.freedesktop.org/drm/drm-misc into drm-intel-next-queued Add support for floating point half-width formats. Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/00b96cd5-91c7-5677-9620-b138c7a92303@linux.intel.com
2019-03-15drm/i915: Precompute/readout/check CHV CGM modeVille Syrjälä
Let's precompute the CGM mode for CHV. And naturally we also read it out and check it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190218193137.22914-3-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2019-03-15drm/i915: Readout and check csc_modeVille Syrjälä
Add the missing readout and PIPE_CONF_CHECK() for csc_mode. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190218193137.22914-2-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2019-03-15drm/i915/icl: remove intel_dpll_is_combophy()Lucas De Marchi
This is only used in intel_display() and shouldn't be needed there. We don't want to keep converting from pll id to pll type so just remove the function. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-6-lucas.demarchi@intel.com
2019-03-13drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi
This exactly same approach was already used from gen9 to gen10 and from gen10 to gen11. Let's also use it for gen11+. Let's first assume that we inherit a similar platform and than we apply the differences on top. Different from the previous attempts this will be done this time with coccinelle. We obviously need to exclude some case that is really exclusive for gen11 like PCH, Firmware, and few others. Luckly this was easy to filter by selecting the files we are touching with coccinelle as exposed below: spatch -sp_file gen11\+.cocci --in-place i915_perf.c \ intel_bios.c intel_cdclk.c intel_ddi.c \ intel_device_info.c intel_display.c intel_dpll_mgr.c \ intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c @noticelake@ expression e; @@ -!IS_ICELAKE(e) +INTEL_GEN(e) < 11 @notgen11@ expression e; @@ -!IS_GEN(e, 11) +INTEL_GEN(e) < 11 @icelake@ expression e; @@ -IS_ICELAKE(e) +INTEL_GEN(e) >= 11 @gen11@ expression e; @@ -IS_GEN(e, 11) +INTEL_GEN(e) >= 11 No functional change. v2: Remove intel_lrc.c per Tvrtko request since those were w/a for ICL hw issuea and media related configuration. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190308214300.25057-1-rodrigo.vivi@intel.com
2019-03-13drm/i915/icl: Implement half float formatsKevin Strasser
64 bpp half float formats are supported on hdr planes only and are subject to the following restrictions: * 90/270 rotation not supported * Yf Tiling not supported * Frame Buffer Compression not supported * Color Keying not supported v2: - Drop handling pixel normalize register - Don't use icl_is_hdr_plane too early v3: - Use refactored icl_is_hdr_plane (Ville) - Use u32 instead of uint32_t (Ville) v6: - Rebase and fix merge conflicts - Reorganize switch statements to keep RGB grouped separately from YUV Cc: Uma Shankar <uma.shankar@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1552437513-22648-4-git-send-email-kevin.strasser@intel.com
2019-03-13drm/i915: Refactor icl_is_hdr_planeKevin Strasser
Change the api in order to enable callers that can't supply a valid intel_plane pointer, as would be the case prior to calling drm_universal_plane_init. v4: - Rename variables and move a declaration (Ville) v6: - Rebase and fix merge conflict Cc: Uma Shankar <uma.shankar@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1552437513-22648-3-git-send-email-kevin.strasser@intel.com
2019-03-11Merge tag 'topic/hdr-formats-2019-03-07' of ↵Joonas Lahtinen
git://anongit.freedesktop.org/drm/drm-misc into drm-intel-next-queued Add support for Y21x and Y41x to drm core and i915, and P01x support to i915. Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f2485309-d645-bed4-95f4-e66ff312aa05@linux.intel.com
2019-03-11drm/i915/icl: Fix CRC mismatch error for DP link layer complianceAditya Swarup
Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows to passthrough FB pixels unmodified across pipe. This fixes the failures for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3. (Lineage #1605353570) v2: This is also needed to fix failing IGT test case kms_cursor_crc on ICL.(Mika Kahola) Make macros consistent with i915_reg.h comments.(Jani Nikula) Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190307021412.18626-1-aditya.swarup@intel.com References: https://bugs.freedesktop.org/show_bug.cgi?id=103232
2019-03-08drm/i915/crc: Make IPS workaround genericJosé Roberto de Souza
Other features like PSR2 also needs to be disabled while getting CRC so lets rename ips_force_disable to crc_enabled, drop all this checks for pipe A and HSW and BDW and make it generic and hsw_compute_ips_config() will take care of all the checks removed from here. v2: Renaming and parameter changes to the functions that prepares the commit (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190308000050.6226-5-jose.souza@intel.com
2019-03-08drm/i915: Compute and commit color features in fastsetsJosé Roberto de Souza
In any commit, intel_modeset_pipe_config() will initialilly clear and then recalculate most of the pipe states but it leave intel specific color features states in reset state. If after intel_pipe_config_compare() is detected that a fastset is possible it will mark update_pipe as true and unsed mode_changed, causing the color features state to be kept in reset state and then latter being committed to hardware disabling the color features. This issue can be reproduced by any code patch that duplicates the actual(with color features already enabled) state and only mark mode_changed as true. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190308000050.6226-3-jose.souza@intel.com
2019-03-06drm/i915: Simplify i830 DVO 2x clock handlingVille Syrjälä
Let's just always enable the DVO 2x clock on i830. This way we don't have to track if DVO is being used or not. The spec does suggest we should disable the clock when it isn't needed, but this does appear to work just fine. This removes another crtc->config usage. v2: Split the DPLL enable sequence change to a separate patch Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190305192400.23121-2-ville.syrjala@linux.intel.com
2019-03-06drm/i915: Do not temporarily disable the DPLL on i830Ville Syrjälä
The current code clears the DPLL register entirely when re-enabling VGA mode temporarily during the DPLL enable sequence. On i830 we want to keep the DPLLs on all the time, so let's not do this temporary disabling. The current code does work, so this doesn't seem super important. But I prefer that we make the behaviour 100% consistent. v2: Split this change the DVO 2x clocking patch Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190305192400.23121-1-ville.syrjala@linux.intel.com
2019-03-05drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planesSwati Sharma
Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1551700595-21481-7-git-send-email-swati2.sharma@intel.com
2019-03-05drm/i915: Preparations for enabling P010, P012, P016 formatsJuha-Pekka Heikkila
Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1551700595-21481-3-git-send-email-swati2.sharma@intel.com
2019-03-04drm/i915: allow platforms without eDP transcoderLucas De Marchi
Define a HAS_TRANSCODER_EDP() macro that checks if we have defined an offset for this transcoder. This allows platforms to be defined without eDP transcoder. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190222230254.20351-2-lucas.demarchi@intel.com
2019-03-04drm/i915: refactor transcoders reporting on error stateLucas De Marchi
Instead of keeping track of the number of transcoders, loop through all the interesting ones and check if there is a correspondent offset. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190222230254.20351-1-lucas.demarchi@intel.com
2019-03-04drm/i915: Fix the state checker for ICL Y planesVille Syrjälä
The plane used to scan out NV12 luma on ICL is logically off but actually on. Fix the state checker to account for this. Cc: Imre Deak <imre.deak@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109457 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190304131217.4338-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2019-02-26drm/i915: Include infoframes in the crtc state dumpVille Syrjälä
Dump out the infoframes in the normal crtc state dump. TODO: Try to better integrate the infoframe dumps with drm state dumps Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190225174106.2163-10-ville.syrjala@linux.intel.com
2019-02-26drm/i915: Check infoframe state in intel_pipe_config_compare()Ville Syrjälä
Check the infoframes and infoframe enable state when comparing two crtc states. We'll use the infoframe logging functions from video/hdmi.c to show the infoframes as part of the state dump. TODO: Try to better integrate the infoframe dumps with drm state dumps v2: drm_printk() is no more Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190225174106.2163-9-ville.syrjala@linux.intel.com
2019-02-21drm/i915/icl: Drop redundant gamma mode maskUma Shankar
gamma mode mask was not considering the 30th and 31st bits. Due to this state readout was masking these bits, causing a mismatch and false warning, even though the registers were updated correctly. Dropped the gamma mode mask as it is redundant and ideally entire register content should be matching. This resolves the state mismatch warnings. Signed-off-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1550689519-6977-1-git-send-email-uma.shankar@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109624
2019-02-20drm/i915: MEI interface implementationRamalingam C
Defining the mei-i915 interface functions and initialization of the interface. v2: Adjust to the new interface changes. [Tomas] Added further debug logs for the failures at MEI i/f. port in hdcp_port data is equipped to handle -ve values. v3: mei comp is matched for global i915 comp master. [Daniel] In hdcp_shim hdcp_protocol() is replaced with const variable. [Daniel] mei wrappers are adjusted as per the i/f change [Daniel] v4: port initialization is done only at hdcp2_init only [Danvet] v5: I915 registers a subcomponent to be matched with mei_hdcp [Daniel] v6: HDCP_disable for all connectors incase of comp_unbind. Tear down HDCP comp interface at i915_unload [Daniel] v7: Component init and fini are moved out of connector ops [Daniel] hdcp_disable is not called from unbind. [Daniel] v8: subcomponent name is dropped as it is already merged. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> [v11] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1550338640-17470-5-git-send-email-ramalingam.c@intel.com
2019-02-20Merge drm/drm-next into drm-intel-next-queuedJoonas Lahtinen
Doing a backmerge to be able to merge topic/mei-hdcp-2019-02-19 PR. Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2019-02-19drm/i915: Move verify_wm_state() to heapChris Wilson
The stack usage exceeded 1024 bytes prompting warnings on conservative setups, so move the temporary allocation for HW readback onto the heap. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190219122215.8941-1-chris@chris-wilson.co.uk
2019-02-18drm/i915: Restore interrupt enabling after a resetChris Wilson
At least on i965g and i965gm, performing a device reset clobbers the IER resulting in loss of interrupts thereafter. So, run the irq_postinstall hook to restore them. v2: Ville pointed out that he already attempted to solve this problem by reinstalling the interrupts in intel_reset_finish() (part of the display handling around reset). However, reinstalling the irq clobbers the i915->irq_mask which we need for handling MI_USER_INTERRUPTS, and does so too late to handle any interrupts generated from resuming the rings. The simple solution to both is to pull the interrupt reenabling from afterwards to around the device reset. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190218153106.16768-1-chris@chris-wilson.co.uk
2019-02-15drm/i915: Wrap plane update/disable hook callsVille Syrjälä
Wrap the .update_plane()/.update_slave()/.disable_plane() vfunc calls into helpers which also take care to emit the appropriate tracepoint. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190206204910.13965-4-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-02-15drm/i915: Add overlooked plane disable tracepoint into ↵Ville Syrjälä
intel_crtc_disable_planes() intel_crtc_disable_planes() disables the planes so it should trigger the appropriate tracepoint. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190206204910.13965-3-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-02-15drm/i915: Add pipe enable/disable tracepointsVille Syrjälä
Add tracepoints for pipe enable/disable. We'll include the frame/scanline counters for all pipes in these tracepoints to help in diagnosing underruns and whatnot when enabling/disabling pipes in parallel with plane updates/flips on another pipe. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190206204910.13965-2-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-02-14Revert "drm/i915: W/A for underruns with WM1+ disabled on icl"Ville Syrjälä
This reverts commit bf002c100740f4ae01d0d86b44f65a712ee14031. The hw team has come up with a better workaround. So let's get rid of this one. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190213165424.22904-1-ville.syrjala@linux.intel.com Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
2019-02-13drm/i915: Apply rps waitboosting for dma_fence_wait_timeout()Chris Wilson
As time goes by, usage of generic ioctls such as drm_syncobj and sync_file are on the increase bypassing i915-specific ioctls like GEM_WAIT. Currently, we only apply waitboosting to our driver ioctls as we track the file/client and account the waitboosting to them. However, since commit 7b92c1bd0540 ("drm/i915: Avoid keeping waitboost active for signaling threads"), we no longer have been applying the client ratelimiting on waitboosts and so that information has only been used for debug tracking. Push the application of waitboosting down to the common i915_request_wait, and apply it to all foreign fence waits as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Eero Tamminen <eero.t.tamminen@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190213092504.25709-1-chris@chris-wilson.co.uk
2019-02-11Merge drm/drm-next into drm-misc-nextMaxime Ripard
We need to backmerge drm-next to fix the komeda build failure. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-11Merge tag 'drm-intel-next-2019-02-07' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - Expose RPCS (SSEU) configuration to userspace for Ice Lake in order to allow userspace to reconfigure the subslice config per context basis. (Tvrtko, Lionel) Driver Changes: - Execbuf and preemption improvements including selftests (Chris) - Rename HAS_GMCH_DISPLAY/HAS_GMCH (Rodrigo) - Debugfs error handling fix for robustness (Greg) - Improve reg_rw traces (Ville) - Push clear_intel_crtc_state onto the heap (Chris) - Watermark fixes for Ice Lake (Ville) - Fix enable count array size and bounds checking (Tvrtko) - MST Fixes (Lyude) - Prevent race and handle error on I915_GEM_MMAP (Joonas) - Initial rework for an full atomic gamma mode (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190208165000.GA30314@intel.com
2019-02-08drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()Ville Syrjälä
On g4x+ we depend on the primary plane DSPCNTR gamma/csc enable bits for the pipe bottom color. To guarantee that those are correct already when enabling the crtc let's do an explicit ->disable_plane() call before enabling the pipe. On skl+ this will be handled by the explicit PIPE_BOTTOM_COLOR register which is already part of the normal color commit we do durign crtc enable. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-8-ville.syrjala@linux.intel.com
2019-02-08drm/i915: Track pipe csc enable in crtc stateVille Syrjälä
Just like we did for pipe gamma, let's also track the pipe csc state. The hardware only exists on ILK+, and currently we always enable it on hsw+ and never on any other platforms. Just like with pipe gamma, the primary plane control register is used for the readout on pre-SKL, and the pipe bottom color register on SKL+. v2: Rebase v3: Allow fastboot with csc_enable changes (Maarten) Deal with HAS_GMCH Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com
2019-02-08drm/i915: Track pipe gamma enable/disable in crtc stateVille Syrjälä
Track whether pipe gamma is enabled or disabled. For now we stick to the current behaviour of always enabling gamma. But we do get working state readout for this now. On SKL+ we use the pipe bottom color as our hardware state. On pre-SKL we read the state back from the primary plane control register. That only really correct for g4x+, as older platforms never gamma correct pipe bottom color. But doing the readout the same way on all platforms is fine, and there is no other way to do it really. v2: Initialize val at declaration (Uma) Drop the bogus skl scaler comment change (Uma) Rebase v3: Allow fastboot with gamma_enable changes (Maarten) v4: Drop the PIPE_BOTTOM_COLOR write from intel_update_pipe_config() again. It snuck back in during the rebase Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207203913.5529-1-ville.syrjala@linux.intel.com
2019-02-08drm/i915: Populate gamma_mode for all platformsVille Syrjälä
On pre-HSW gamma mode is configured via PIPECONF. The bits are the same except shifted up, so we can reuse just store them in crtc_state->gamma_mode in the HSW+ way, allowing us to share some code later. v2: Allow fastboot with gamma_mode changes (Maarten) Add space around the '<<' in the reg macro Deal with HAS_GMCH Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-2-ville.syrjala@linux.intel.com
2019-02-07drm/i915: prepare for drmP.h removal from drm_modeset_helper.hSam Ravnborg
The use of drmP.h is discouraged and removal of it from drm_modeset_helper.h caused i915 to fail to build. This patch introduce the necessary fixes to prepare for the drmP.h removal from drm_modeset_helper.h. In the files touched the lists of include files was grouped and sorted. Build tested on x86 and arm allmodconfig / allyesconfig. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: intel-gfx@lists.freedesktop.org Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190126122527.11647-3-sam@ravnborg.org
2019-02-07drm/i915: Move LUT programming to happen after vblank waitsVille Syrjälä
The LUTs are single buffered so we should program them after the double buffered pipe updates have been latched by the hardware. We'll also fix up the IPS vs. split gamma w/a to do the IPS disable like everyone else. Note that this is currently dead code as we don't use the split gamma mode on HSW, but that will be fixed up shortly. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-7-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2019-02-07drm/i915: Split color mgmt based on single vs. double buffered registersVille Syrjälä
Split the color management hooks along the single vs. double buffered registers line. Of the currently programmed registers GAMMA_MODE and the ilk+ pipe CSC are double buffered, the LUTS and CHV CGM block are single buffered. The double buffered register will be programmed during the normal pipe update with evasion, and also during pipe enable so that the settings will already be correct when the pipe starts up before the planes are enabled. The single buffered registers are currently programmed before the vblank evade. Which is totally wrong, but we'll correct that later. v2: Add some docs to explain the two vfuncs (Matt,Uma) Rebase Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-6-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2019-02-07drm/i915: Split the gamma/csc enable bits from the plane_ctl() functionVille Syrjälä
On g4x+ the pipe gamma enable bit for the primary plane affects the pipe bottom color as well. The same for the pipe csc enable bit on ilk+. Thus we must configure those bits correctly even when the primary plane is disabled. To make the feasible let's split those settings from the plane_ctl() function into a seprate funciton that we can call from the ->disable_plane() hook as well. For consistency we'll do that on all the plane types. While that has no real benefits at this time, it'll become useful when we start to control the pipe gamma/csc enable bits dynamically when we overhaul the color management code. On pre-g4x there doesn't appear to be any way to gamma correct the pipe bottom color, but sticking to the same pattern doesn't hurt. And it'll still help us to do crtc state readout correctly for the pipe gamma enable bit for the color management overhaul. An alternative apporach would be to still precompute these bits into plane_state->ctl, but that would require that we run through the plane check even when the plane isn't logically enabled on any crtc. Currently that condition causes us to short circuit the entire thing and not call ->check_plane(). There would also be some chicken and egg problems with ->check_plane() vs. crtc color state check that would requite splitting certain things into multiple steps. So all in all this seems like the easier route. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-2-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 21:57:55 +0000