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path: root/drivers/gpu/drm/i915/i915_reg.h
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2021-03-24drm/i915: reserve stolen for LMEM regionCQ Tang
The lmem region needs to remove the stolen part, which should just be a case of snipping it off the end. Signed-off-by: CQ Tang <cq.tang@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-3-matthew.auld@intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2021-03-12drm/i915: Workaround async flip + VT-d corruption on HSW/BDWVille Syrjälä
On HSW/BDW with VT-d active the first tile row scanned out after the first async flip of the frame often ends up corrupted. Whether the corruption happens or not depends on the scanline on which the async flip happens, but the behaviour seems very consistent. Ie. the same set of scanlines (which are most scanlines) always show the corruption. And another set of scanlines (far less of them) never shows the corruption. I discovered that disabling the fetch-stride stretching feature cures the corruption. This is some kind of TLB related prefetch thing AFAIK. We already disable it on SNB primary planes due to a documented workaround. The hardware folks indicated that disabling this should be fine, so let's go with that. And while we're here, let's document the relevant bits on all pre-skl platforms. Fixes: 2a636e240c77 ("drm/i915: Implement async flip for ivb/hsw") Fixes: cda195f13abd ("drm/i915: Implement async flips for bdw") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210220103303.3448-1-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-03-11Merge drm/drm-next into drm-intel-nextJani Nikula
Sync up with upstream. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2021-02-22drm/i915/reg: add stream splitter configuration definitionsJani Nikula
The splitter configuration is required for eDP MSO. Bspec: 50174 Cc: Nischal Varide <nischal.varide@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/443ad1fbf908800ee4e09315cb6a7ba26c64d136.1613054234.git.jani.nikula@intel.com
2021-02-08drm/i915: Disable atomics in L3 for gen9Chris Wilson
Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as the machine stops responding milliseconds after receipt of the reset request [GDRT]. By disabling the cached atomics, the hang do not occur and we presume the GPU would reset normally for similar hangs. Sadly this is a shotgun approach, but since the impact is critical it is better to err on the safe side and work back from there. Reported-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Jason Ekstrand <jason@jlesktrand.net> Link: https://patchwork.freedesktop.org/patch/msgid/20210125220152.24070-1-chris@chris-wilson.co.uk Cc: stable@vger.kernel.org (cherry picked from commit b267c7ae0ad5b437b068f46919b17f85000154b4) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2021-02-02Merge tag 'topic/adl-s-enabling-2021-02-01-1' of ↵Jani Nikula
git://anongit.freedesktop.org/drm/drm-intel into drm-intel-next Driver Changes: - Add basic support for Alder Lake S, to be shared between drm-intel-next and drm-intel-gt-next Signed-off-by: Jani Nikula <jani.nikula@intel.com> # Conflicts: # drivers/gpu/drm/i915/i915_drv.h From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210202025620.2212559-1-lucas.demarchi@intel.com
2021-01-29drm/i915: Implement async flips for vlv/chvVille Syrjälä
Add support for async flips on vlv/chv. Unlike all the other platforms vlv/chv do not use the async flip bit in DSPCNTR and instead we select between async vs. sync flips based on the surface address register. The normal DSPSURF generates sync flips DSPADDR_VLV generates async flips. And as usual the interrupt bits are different from the other platforms. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-12-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-29drm/i915: Implement async flips for bdwVille Syrjälä
Implement async flip support for BDW. The implementation is similar to the skl+ code. And just like skl/bxt/glk bdw also needs the disable w/a, thus we need to plumb the desired state of the async flip all the way down to i9xx_plane_ctl_crtc(). According to the spec we do need to bump the surface alignment to 256KiB for this. Async flips require an X-tiled buffer so we don't have to worry about linear. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-9-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup
Add changes to configure port clock registers for ADL-S. Combo phy port clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers. The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S translates to DDI A -> DDIA DDI B -> USBC1 DDI I -> USBC2 For DPCLKA_CFGCR1 DDI J -> USBC3 DDI K -> USBC4 Bspec: 50287 Bspec: 53812 Bspec: 53723 v2: Replace I915_READ() with intel_de_read().(Jani) v3: - Use reg variable to assign ADLS specific registers inorder to replace branching with intel_de_read/write() calls.(mdroper) - Reuse icl_get_ddi_pll() for ADLS to fix issue with updating active dpll on driver load.(aswarup) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-7-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup
Add changes for configuring DPLL for ADL-S - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S - Extend CNL macro to choose DPLL_ENABLE for ADL-S. - Select CFGCR0 and CFGCR1 for ADL-S plls. On BSpec: 53720 PLL arrangement dig for adls: DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1) DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1) v2 (Lucas): add missing update_ref_clks Bspec: 50288 Bspec: 50289 Bspec: 49443 v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield for DPLL3_USED.(mdroper) Bspec: 53707 v4: BSpec 53723 has been updated with note - DPLL2 is controlled by DPLL4 CFGCR 0/1.(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-6-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Add PHYs for Alderlake SAnusha Srivatsa
Alderlake-S has 5 combo phys, add reg definitions for combo phys and update the port to phy helper for ADL-S. v2: - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc() and return false for platforms RKL,DG1 and ADLS.(mdroper) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-5-aditya.swarup@intel.com
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä
Give the pipeline full line count bits more descriptive names Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-9-manasi.d.navare@intel.com
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada
Render Decompression is supported with Y-Tiled main surface. The CCS is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. Additional Clear Color information is passed from the user-space through an offset in the GEM BO. Add a new modifier to identify and parse new Clear Color information and extend Gen12 render decompression functionality to the newly added modifier. v2: Fix has_alpha flag for modifiers, omit CC modifier during initial plane config(Matt). Fix Lookup error. v3: Fix the panic while running kms_cube v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt) v5: Fix typos and wrap comments(Matt) v6: - Use format block descriptors to get the subsampling calculations for the CCS surface right. - Use helpers to convert between main and CCS surfaces. - Prevent coordinate checks for the CC surface. - Simplify reading CC value from surface map, add description of CC val layout. - Remove redundant ccval variable from skl_program_plane(). v7: - Move the CC value readout after syncing against any GPU write on the FB obj (Nanley, Chris) - Make sure the CC value readout works on platforms w/o struct pages (dGFX) and other non-coherent platforms wrt. CPU reads (none atm). (Chris) v8: - Rebase on the function param order change of i915_gem_object_read_from_page(). - Clarify code comment on the clear color value format and the required FB obj pinning/syncing by the caller. - Remove redundant variables in intel_atomic_prepare_plane_clear_colors(). v9: - Fix s/sizeof(&ccval)/sizeof(ccval)/ typo. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115213952.1040398-1-imre.deak@intel.com
2021-01-13drm/i915/hdcp: Add HDCP 2.2 stream registerAnshuman Gupta
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. B.Spec: 21780 B.Spec: 14410 B.Spec: 50573 v2 - Modified naming convention of HDCP2_STREAM_STATUS for pre-gen12 platforms inline with B.Spec. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111081120.28417-17-anshuman.gupta@intel.com
2021-01-13drm/i915/hdcp: HDCP stream encryption supportAnshuman Gupta
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP encryption over DP MST Transport Link. HDCP 1.4 stream encryption requires to validate the stream encryption status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link in order to enable/disable the stream encryption. Both of above requirement are same for all Gen with respect to B.Spec Documentation. v2: - Cosmetic changes function name, error msg print and stream typo fixes. [Uma] v3: - uniformity for connector detail in DMESG. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111081120.28417-8-anshuman.gupta@intel.com
2021-01-11drm/i915: Fix HTI port checkingJosé Roberto de Souza
There was some misinterpretation of specification, when DDIX_USED is set, the next bit means 0 for DP and 1 for HDMI. Anyways this misinterpretation is not causing any issues, this change is just to comply with specification. Also as for us it do not matters if it is HDMI or DP, not checking the port type that HTI is using. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210108134802.21280-1-jose.souza@intel.com
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of ↵Daniel Vetter
git://anongit.freedesktop.org/drm/drm-intel into drm-next - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani) - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210104211018.GA1094707@intel.com
2020-12-03drm/i915: Add VRR_CTL_LINE_COUNT field to VRR_CTL register defManasi Navare
VRR_CTL register only had a GENMASK but no field prep define for TRANS_VRR_CTL_LINE_COUNT field so add that Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201202182727.26158-1-manasi.d.navare@intel.com
2020-12-03Merge tag 'drm-intel-next-queued-2020-11-27' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 features for v5.11: Highlights: - Enable big joiner to join two pipes to one port to overcome pipe restrictions (Manasi, Ville, Maarten) Display: - More DG1 enabling (Lucas, Aditya) - Fixes to cases without display (Lucas, José, Jani) - Initial PSR state improvements (José) - JSL eDP vswing updates (Tejas) - Handle EDID declared max 16 bpc (Ville) - Display refactoring (Ville) Other: - GVT features - Backmerge Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87czzzkk1s.fsf@intel.com
2020-12-02drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()Jani Nikula
Good riddance! Remove the macros and their remaining references in comments. The following functions should be used instead, depending on the use case: - intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read() - intel_de_read(), intel_de_write(), intel_de_posting_read() Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201130111601.2817-10-jani.nikula@intel.com
2020-11-19drm/i915/perf: workaround register corruption in OATAILPTRLionel Landwerlin
After having written the entire OA buffer with reports, the HW will write again at the beginning of the OA buffer. It'll indicate it by setting the WRAP bits in the OASTATUS register. When a wrap happens and that at the end of the read vfunc we write the OASTATUS register back to clear the REPORT_LOST bit, we sometimes see that the OATAILPTR register is reset to a previous position on Gen8/9 (apparently not the case on Gen11+). This leads the next call to the read vfunc to process reports we've already read. Because we've marked those as read by clearing the reason & timestamp dwords, they're discarded and a "Skipping spurious, invalid OA report" message is emitted. The workaround to avoid this OATAILPTR value reset seems to be to set the wrap bits when writing back OASTATUS. This change has no impact on userspace, it only avoids a bunch of DRM_NOTE("Skipping spurious, invalid OA report\n") messages. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+") Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201117130124.829979-1-lionel.g.landwerlin@intel.com
2020-11-13Merge tag 'drm-intel-gt-next-2020-11-12-1' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next Cross-subsystem Changes: - DMA mapped scatterlist fixes in i915 to unblock merging of https://lkml.org/lkml/2020/9/27/70 (Tvrtko, Tom) Driver Changes: - Fix for user reported issue #2381 (Graphical output stops with "switching to inteldrmfb from simple"): Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init (Ville, Chris) - Fix for Tigerlake (and earlier) to avoid spurious empty CSB events leading to hang (Chris, Bruce) - Delay execlist processing for Tigerlake to avoid hang (Chris) - Fix for Tigerlake RCS engine health check through heartbeat (Chris) - Fix for Tigerlake reserved MOCS entries (Ayaz, Chris) - Fix Media power gate sequence on Tigerlake (Rodrigo) - Enable eLLC caching of display buffers for SKL+ (Ville) - Support parsing of oversize batches on Gen9 (Matt, Chris) - Exclude low pages (128KiB) of stolen from use to avoid thrashing during reset (Chris) - Flush engines before Tigerlake breadcrumbs (Chris) - Use the local HWSP offset during submission (Chris) - Flush coherency domains on first set-domain-ioctl (Chris, Zbigniew) - Use the active reference on the vma while capturing to avoid use-after-free (Chris) - Fix MOCS PTE setting for gen9+ (Ville) - Avoid NULL dereference on IPS driver callback while unbinding i915 (Chris) - Avoid NULL dereference from PT/PD stash allocation error (Matt) - Hold request reference for canceling an active context (Chris) - Avoid infinite loop on x86-32 when mapping a lot of objects (Chris) - Disallow WC mappings when processor doesn't support them (Chris) - Return correct error in i915_gem_object_copy_blt() error path (Dan) - Return correct error in intel_context_create_request() error path (Maarten) - Tune down GuC communication enabled/disabled messages to debug (Jani) - Fix rebased commit "Remove i915_request.lock requirement for execution callbacks" (Chris) - Cancel outstanding work after disabling heartbeats on an engine (Chris) - Signal cancelled requests (Chris) - Retire cancelled requests on unload (Chris) - Scrub HW state on driver remove (Chris) - Undo forced context restores after trivial preemptions (Chris) - Handle PCI unbind in PMU code (Tvrtko) - Fix CPU hotplug with multiple GPUs in PMU code (Trtkko) - Correctly set SFC capability for video engines (Venkata) - Update GuC code to use firmware v49.0.1 (John, Matthew B., Daniele, Oscar, Michel, Rodrigo, Michal) - Improve GuC warnings on loading failure (John) - Avoid ownership race in buffer pool by clearing age (Chris) - Use MMIO to read CSB in case of failure (Chris, Mika) - Show engine properties in engine state dump to indicate changes (Chris, Joonas) - Break up error capture compression loops with cond_resched() (Chris) - Reduce GPU error capture mutex hold time to avoid khungtaskd (Chris) - Serialise debugfs i915_gem_objects with ctx->mutex (Chris) - Always test execution status on closing the context and close if not persistent (Chris) - Avoid mixing integer types during batch copies (Chris, Jared) - Skip over MI_NOOP when parsing to avoid overhead (Chris) - Hold onto an explicit ref to i915_vma_work.pinned (Chris) - Perform all asynchronous waits prior to marking payload start (Chris) - Pull phys pread/pwrite implementations to the backend (Matt) - Improve record of hung engines in error state (Tvrtko) - Allow backends to override pread implementation (Matt) - Reinforce LRC poisoning checks to confirm context survives execution (Chris) - Fix memory region max size calculation (Matt) - Fix order when adding blocks to memory region (Matt) - Eliminate unused intel_virtual_engine_get_sibling func (Chris) - Cleanup kasan warning for on-stack (unsigned long) casting (Chris) - Onion unwind for scratch page allocation failure (Chris) - Poison stolen pages before use (Chris) - Selftest improvements (Chris) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201112163407.GA20320@jlahtine-mobl.ger.corp.intel.com
2020-11-11drm/i915/tgl: Fix Media power gate sequence.Rodrigo Vivi
Some media power gates are disabled by default. commit 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating") tried to enable it, but it duplicated an existent register. So, the main PG setup sequences ended up overwriting it. So, let's now merge this to the main PG setup sequence. v2: (Chris): s/BIT/REG_BIT, remove useless comment, remove useless =0, use the right gt, remove rc6 sequence doubt from commit message. Fixes: 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: stable@vger.kernel.org#v5.5+ Cc: Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20201111072859.1186070-1-rodrigo.vivi@intel.com
2020-11-09drm/i915/dg1: map/unmap pll clocksLucas De Marchi
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a single macro that chooses the correct register according to the phy being accessed, use the correct bitfields for each pll/phy and implement separate functions for DG1 since it doesn't share much with ICL/TGL anymore. The previous values were correct for PHY A and B since they were using the same register as before and the bitfields were matching. v2: Add comment and try to simplify DG1_DPCLKA* macros by reusing previous ones v3: - Fix DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK() after wrong macro reuse - Move phy -> id map to a separate macro (Aditya) - Remove DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK where not required (Aditya) - Use drm_WARN_ON Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201106210006.837953-1-lucas.demarchi@intel.com
2020-10-30drm/i915: Enable hpd logic only for ports that are presentVille Syrjälä
Let's enable the hardware hpd logic only for the ports we can actually use. In theory this may save some miniscule amounts of power, and more importantly it eliminates a lot if platform specific codepaths since the generic thing can now deal with any combination of ports being present on each SKU. v2: Deal with DG1 v3: Deal with DG1 some more Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-18-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2020-10-30drm/i915: Remove per-platform IIR HPD maskingVille Syrjälä
We no longer unmask all HPD irqs, so we can drop the ugly per-platform HPD IIR masking. IMR will prevent unsupported bits from appearing in IIR. v2: Deal with DG1 Include "HOTPLUG" in the mask names (Lucas) v3: Fix typos in subject Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-17-ville.syrjala@linux.intel.com
2020-10-30drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bitsVille Syrjälä
Parametrize the icp+ TC HPD bits using hpd_pin rather than tc_port so it's clear what kind of an animal we're dealing with. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-12-ville.syrjala@linux.intel.com
2020-10-30drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()Ville Syrjälä
Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG() to make it clear what they refer to. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-11-ville.syrjala@linux.intel.com
2020-10-30drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bitsVille Syrjälä
Use hpd_pin instead of port in the parametrized ICP+ DDI HPD macros. Makes it clear what these refer to. v2: Handle DG1 Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-10-ville.syrjala@linux.intel.com
2020-10-30drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()Ville Syrjälä
Unify the BDW/BXT hotplug bits. BDW only has port A, but that matches BXT port A so we can shar the same macro for both. v2: Remember the gvt Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-9-ville.syrjala@linux.intel.com
2020-10-30drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pinVille Syrjälä
Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear these have nothing to do with DDI ports or PHYs as such. The only thing that matters is the HPD pin assignment. v2: Remember the gvt Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-8-ville.syrjala@linux.intel.com
2020-10-30drm/i915: s/PORT_TC/TC_PORT_/Ville Syrjälä
Make the namespacing for enum tc_port better by adding the TC_ to the actual enum values. v2: Drop the extra TC (Lucas) Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-2-ville.syrjala@linux.intel.com
2020-10-29drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registersVille Syrjälä
Remove the hand rolled array of WM0_PIPE register offsets and use the standard _MMIO_PIPE3() instead. v2: Take care of gvt too Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181212211738.27770-1-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2020-10-23drm/i915/dg1: invert HPD pinsClinton A Taylor
HPD pins are inverted for DG1 platform. Bspec: 49956 Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201021082034.3170478-3-lucas.demarchi@intel.com
2020-10-23drm/i915/dg1: add hpd interrupt handlingLucas De Marchi
DG1 has one more combo phy port, no TC and all irq handling goes through SDE, like for MCC. v2: Also change intel_hpd_pin_default() to include DG1 mapping v3, v4: Rebase on hpd refactor Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201021082034.3170478-2-lucas.demarchi@intel.com
2020-10-21drm/i915: Introduce scaling filter related registers and bit fieldsPankaj Bharadiya
Introduce scaler registers and bit fields needed to configure the scaling filter in prgrammed mode and configure scaling filter coefficients. changes since v3: * None changes since v2: * Change macro names to CNL_* and use +(set)*8 instead of adding another trip through _PICK_EVEN (Ville). changes since v1: * None changes since RFC: * Parametrize scaler coeffient macros by 'set' (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201020161427.6941-3-pankaj.laxminarayan.bharadiya@intel.com
2020-10-20drm/i915: Sort the mess around ICP TC hotplugs regsVille Syrjälä
Move the DSC stuff out from the middle of the ICP HPD register definitions. The location seems to have been selected by a dice roll. SHPD_FILTER_CNT addition also went astray due to the DSC mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201006143349.5561-2-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2020-10-19drm/i915/display: Program DBUF_CTL tracker state serviceJosé Roberto de Souza
This sequence is not part of "Sequences to Initialize Display" but as noted in the MBus page the DBUF_CTL.Tracker_state_service needs to be set to 8. BSpec: 49213 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201019173906.18892-1-jose.souza@intel.com
2020-10-15drm/i915/dg1: Update DMC_DEBUG registerAnshuman Gupta
Update the DMC_DEBUG_DC5 register to its new location and do not try reading the DC6 counter since DG1 doesn't support DC6. v2: Use IS_DGFX() instead of IS_DG1(). Even if not having DC6 is not directly related to DGFX, the register move to a new location is. So in future, if there is one supporting DC6, it would just need to add the other register rather than fixing the case of a wrong register being read (Matt) Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-10-lucas.demarchi@intel.com
2020-10-15drm/i915/dg1: Add initial DG1 workaroundsStuart Summers
DG1 shares some workarounds with TGL and RKL and also has some additional workarounds of its own. v2: Correct location of Wa_1408615072 (JohnH). v3: Apply WAs 1606700617, 18011464164 and 22010931296 to DG1 (José) v4 (Anusha) - Add Wa_22010271021 - s/Wa_14010096844/Wa_1409836686 v5: - Extend Wa_14010919138 to all revs (Matt Atwood) - Power gate media is global gen12 design. (Rodrigo) - Rebase (Lucas) v6: use REG_BIT() to fix checkpatch warning (Lucas) BSpec: 53508 Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-8-lucas.demarchi@intel.com
2020-10-15drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi
Add DG1 DPLL Enable register macro and use the macro to enable the correct DPLL based on PLL id. Although we use _MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys. While at it, fix coding style: wrong newlines and use if/else chain v2: Rewrite original patch from Aditya Swarup based on refactors upstream Bspec: 49443, 49206 Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-6-lucas.demarchi@intel.com
2020-10-15drm/i915/dg1: Add DPLL macros for DG1Aditya Swarup
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and DPLL2 and DPLL3 drive DDI-TC1/DDI-TC2. Introduce DG1_DPLL_CFCRx() helper macros to configure DPLL registers. Bspec: 50288, 50299 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-4-lucas.demarchi@intel.com
2020-10-09drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GTMatt Roper
The power well that we've been referring to as the 'blitter' well is actually more of a general GT power well which contains a lot of things other than the blitter engine registers. The FORCEWAKE_BLITTER name in the code was used for historic reasons, but no longer matches how the bspec describes this power well and just causes confusion for people not familiar with this area of the code. Let's rename it to FORCEWAKE_GT to more accurately describe the role of the power well and match how the modern bspec refers to it. v2: - Add a comment noting that the GT power well includes the blitter engine. (Jose) Bspec: 66696, 66534, 67609 Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201009194442.3668677-2-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak
The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1 WRPLL parameters (assuming PDIV=7 was the intended setting). This corresponds to 262749 PLL frequency/port clock. Later the driver sets the same mode for which it calculates the same dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding). Based on the above, let's assume that PDIV=7 was intended and the HW just ignores bit#0 in the PDIV register field for this setting, treating 100b and 101b encodings the same way. While at it add the MISSING_CASE() for the p0,p2 divider decodings. v2: (Ville) - Add a define for the incorrect divider value. - Emit only a debug message when detecting the incorrect divider value. - Use fallthrough from the incorrect divider value case. - Add the MISSING_CASE()s. v3: Return 0 freq for incorrect divider values. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201006013555.1488262-1-imre.deak@intel.com
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper
DG1 does some additional pcode/uncore handshaking at boot time; this handshaking must complete before various other pcode commands are effective and before general work is submitted to the GPU. We need to poll a new pcode mailbox during startup until it reports that this handshaking is complete. The bspec doesn't give guidance on how long we may need to wait for this handshaking to complete. For now, let's just set a really long timeout; if we still don't get a completion status by the end of that timeout, we'll just continue on and hope for the best. v2 (Lucas): Rename macros to make clear the relation between command and result (requested by José) Bspec: 52065 Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201001063917.3133475-2-lucas.demarchi@intel.com
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä
Implement display w/a #1142. This supposedly fixes some underruns with FBC+VTd. Bspec says we should use the same programming regardless of circumstances. Apparently we should flip the magic bits before turning on any planes so let's put this into the early w/as. Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200924194810.10293-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-28drm/i915: Relocate CHV CGM gamma masksVille Syrjälä
CGM_PIPE_GAMMA_RED_MASK & co. are misplaced. Move then below the relevant register. And while at it add the degamma counterparts. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-8-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Add support for async flips in I915Karthik B S
Set the Async Address Update Enable bit in plane ctl when async flip is requested. v2: -Move the Async flip enablement to individual patch (Paulo) v3: -Rebased. v4: -Add separate plane hook for async flip case (Ville) v5: -Rebased. v6: -Move the plane hook to separate patch. (Paulo) -Remove the early return in skl_plane_ctl. (Paulo) v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville) v8: -Rebased. v9: -Rebased. v10: -Rebased. Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-3-karthik.b.s@intel.com
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä
We have nice parametrized GEN11_{TC,TBT}_HOTPLUG() so nuke the overlapping defines. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-7-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-11drm/i915: Nuke dpio_phy_iosf_port[]Ville Syrjälä
There's no real reason to stash away the DPIO PHY IOSF sideband port numbers for VLV/CHV. Just compute them at runtime in the sideband code. Gets rid of the oddball intel_init_dpio() function from the high level init flow. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200907162709.29579-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-03 08:17:07 +0000