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path: root/drivers/gpu/drm/i915/display/intel_display.c
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2024-02-27drm/i915/dp: Use drm_dp_max_dprx_data_rate()Imre Deak
Instead of intel_dp_max_data_rate() use the equivalent drm_dp_max_dprx_data_rate() which was copied from the former one in a previous patch. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240220211841.448846-6-imre.deak@intel.com
2024-02-27drm/i915/dp: Add support to notify MST connectors to retry modesetsImre Deak
On shared (Thunderbolt) links with DP tunnels, the modeset may need to be retried on all connectors on the link due to a link BW limitation arising only after the atomic check phase. To support this add a helper function queuing a work to retry the modeset on a given port's connector and at the same time any MST connector with streams through the same port. A follow-up change enabling the DP tunnel Bandwidth Allocation Mode will take this into use. v2: - Send the uevent only to enabled MST connectors. (Jouni) Cc: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240220211841.448846-5-imre.deak@intel.com
2024-02-27drm/i915: Fix display bpp limit computation during system resumeImre Deak
The system resume display mode restoration should happen with an output configuration matching that of the suspend time saved mode. Since the restored mode configuration is subject to the bpp fallback logic, starting out with an unlimited bpp and reducing the bpp as required by any (MST) link BW limit, the resulting bpp will match the one during suspend only if the BW limit checks during suspend and resume are applied in an identical way. The latter is not guaranteed at the moment, since the pre-suspend MST topology may not be in place during resume (for instance if the MST sink was disconnected while being suspended), which makes the MST link BW check accept the unlimited bpp mode configuration unconditionally without ensuring that the required BW fits into the available MST link BW. To fix the above, initialize the bpp fallback logic with the max link bpp / force-FEC limits left behind by the suspend time mode save. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240220211841.448846-4-imre.deak@intel.com
2024-02-16Merge tag 'drm-misc-next-2024-02-15' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v6.9: UAPI Changes: Cross-subsystem Changes: arch: - powerpc/ps3: select CONFIG_VIDEO Core Changes: ci: - msm: fix apq8016 runner display: - use newer DRM print helpers documentation: - fix typos print: - add device-specific error and debug printers sysfb: - set Linux parent device for firmware framebuffer tests: - mm: use newer DRM print helpers Driver Changes: bridge: - switch to ->read_edid callback throughout the bridge drivers - remove old ->get_edid callback i915: - use newer DRM print helpers lima: - improve stability by fixes to error handling and recovery mediathek: - switch to ->read_edid callback msm: - switch to ->read_edid callback omap: - switch to ->read_edid callback panel: - add Powkiddy RGB10MAX3 plus DT bindings - st7703: support panel rotation plus DT bindings rockchip: - DT bindings: remove port, add power-domains xe: - use newer DRM print helpers xlnx: - switch to ->read_edid callback Signed-off-by: Dave Airlie <airlied@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEchf7rIzpz2NEoWjlaA3BHVMLeiMFAmXOD/oACgkQaA3BHVML # eiMWMAgArTVXF4UQ+FUxYZB5QTm2veYIpilvwmzaQLNxsM9SsWpzwMIVAi+xf93g # uqUqkl6QvZ9pJg6bxuXRNcJw/GObIO4x6tn+LkbccczgHiHwvn6ydNdUoMx8ulne # EsGC0z8bb5Gpwh9b/pnBul2AoIE7PHAJltgH271/O2xnhFMUbchQ0ckHvWnn8/GA # Nef145ySX4gkYtY8u2TRr4r6Bkp7Tpiyv6ipU7Cpu7KqyveTDMx3c9r5FaiHnJT/ # Hx/5s87q0Bx2m+iNjlBLJzYjF2UWth+pbfiu3xwyWOE7hdkPLwCQ5mqHWcFFqxfb # Vuj9jP+Vb68L7EvGpq2LArLdhZjHIQ== # =SsjX # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Feb 2024 23:22:02 AEST # gpg: using RSA key 7217FBAC8CE9CF6344A168E5680DC11D530B7A23 # gpg: Can't check signature: No public key From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20240215132610.GA1464@localhost.localdomain
2024-02-15drm/i915: Enable fastboot across the boardVille Syrjälä
There's nothing magical about vlv+ platforms vs. fastboot. If it works somewhere it should work everywhere, assuming we've not missed any crucial state checks. That seems unlikely on older platforms with less state to check anyway. Just enable fastboot across the board, and the remove the remnants of the optional stuff (we already removed the modparam for fastboot anyway). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240209183809.16887-6-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2024-02-15drm/i915: Add PLL .compare_hw_state() vfuncVille Syrjälä
Chunk up the humongous dpll_hw_state comparison check into per-platform variants, implemented in the dpll_mgr. This is step one in allowing each platform (or perhaps even PLL) type to have a custom hw state structure instead of having to smash it all into one. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240209183809.16887-5-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2024-02-15drm/i915: Include the CRTC name in the ELD buffer mismatchVille Syrjälä
Most crtc state mismatches include the CRTC id+name in the prints. Also include it in the ELD buffer mismatch prints. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240209183809.16887-3-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2024-02-15drm/i915: Fix PLL state check for gmch platformsVille Syrjälä
GMCH DPLL state check was mistakenly removed in commit 87fc875a2b85 ("drm/i915/dg2: Skip shared DPLL handling"). Bring it back. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240209183809.16887-2-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2024-02-09drm/dp: switch drm_dp_vsc_sdp_log() to struct drm_printerJani Nikula
Use the existing drm printer infrastructure instead of local macros. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/cdf8faf272d345de215feb6ececba384ecaecdb4.1705410327.git.jani.nikula@intel.com
2024-02-07drm/i915: Try to relocate the BIOS fb to the start of ggttVille Syrjälä
On MTL the GOP (for whatever reason) likes to bind its framebuffer high up in the ggtt address space. This can conflict with whatever ggtt_reserve_guc_top() is trying to do, and the result is that ggtt_reserve_guc_top() fails and then we proceed to explode when trying to tear down the driver. Thus far I haven't analyzed what causes the actual fireworks, but it's not super important as even if it didn't explode we'd still fail the driver load and the user would be left with an unusable GPU. To remedy this (without having to figure out exactly what ggtt_reserve_guc_top() is trying to achieve) we can attempt to relocate the BIOS framebuffer to a lower ggtt address. We can do this at this early point in driver init because nothing else is supposed to be clobbering the ggtt yet. So we simply change where in the ggtt we pin the vma, the original PTEs will be left as is, and the new PTEs will get written with the same dma addresses. The plane will keep on scanning out from the original PTEs until we are done with the whole process, and at that point we rewrite the plane's surface address register to point at the new ggtt address. Since we don't need a specific ggtt address for the plane (apart from needing it to land in the mappable region for normal stolen objects) we'll just try to pin it without a fixed offset first. It should end up at the lowest available address (which really should be 0 at this point in the driver init). If that fails we'll fall back to just pinning it exactly to the origianal address. To make sure we don't accidentlally pin it partially over the original ggtt range (as that would corrupt the original PTEs) we reserve the original range temporarily during this process. v2: Try to pin explicitly to ggtt offset 0 as otherwise DG2 puts it even higher (atm we have no PIN_LOW flag to force it low) v3: "fix" xe Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Tested-by: Paz Zcharya <pazz@chromium.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240202224340.30647-16-ville.syrjala@linux.intel.com Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
2024-02-02drm/i915: Extract intel_atomic_swap_state()Ville Syrjälä
Pull all the state swap stuff into its own function to declutter intel_atomic_commit() a bit. Note that currently the state swap is spread across both sides of the unprepare branch in intel_atomic_commit(), but we can pull all of it ahead a bit since we bail on the first error, and thus there is no change in behaviour from the reordering. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219130756.25986-4-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2024-02-02drm/i915: Rework global state serializaitonVille Syrjälä
Instead of injecting extra crtc commits to serialize the global state let's hand roll a bit of commit machinery to take care of the hardware synchronization. Rather than basing everything on the crtc commits we track these as their own thing. I think this makes more sense as the hardware blocks we are working with are not in any way tied to the pipes, so the completion should not be tied in with the vblank machinery either. The difference to the old behaviour is that: - we no longer pull extra crtcs into the commit which should make drm_atomic_check_only() happier - since those crtcs don't get pulled in we also don't end up reprogamming them and thus don't need to wait their vblanks to pass/etc. So this should be tad faster as well. TODO: perhaps have each global object complete its own commit once the post-plane update phase is done? Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6728 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219130756.25986-3-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2024-01-15Merge drm/drm-next into drm-intel-nextJani Nikula
Backmerge to bring Xe driver to drm-intel-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-01-15drm/i915/display: No need for full modeset due to psrJouni Högander
There is no specific reason to force full modeset if psr is enabled. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Tested-by: Paz Zcharya <pazz@chromium.org> Reviewed-by: Stanislav Lisovskiy <staniskav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240109100517.1947414-2-jouni.hogander@intel.com
2024-01-09drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transportJouni Högander
There is a new register used to configure selective update area size for early transport. Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area carried in crtc_state->su_area. Bspec: 68927 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-6-jouni.hogander@intel.com
2024-01-08drm/i915: Prevent modesets during driver init/shutdownImre Deak
An unexpected modeset or connector detection by a user (user space or FB console) during the initialization/shutdown sequence is possible either via a hotplug IRQ handling work or via the connector sysfs (status/detect) interface. These modesets/detections should be prevented by disabling/flushing all related hotplug handling work and unregistering the interfaces that can start them at the beginning of the shutdown sequence. Some of this - disabling all related intel_hotplug work - will be done by the next patch, but others - for instance disabling the MST hotplug works - require a bigger rework. It makes sense - for diagnostic purpose, even with all the above work and interface disabled - to detect and reject any such user access. This patch does that for modeset accesses and a follow-up patch for connector detection. During driver loading/unloading/system suspend/shutdown and during system resume after calling intel_display_driver_disable_user_access() or intel_display_driver_resume_access() correspondigly, the current thread is allowed to modeset (as this thread requires to do an initial/restoring modeset or a disabling modeset), other threads (the user threads) are not allowed to modeset. During driver loading/system resume after calling intel_display_driver_enable_user_access() all threads are allowed to modeset. During driver unloading/system suspend/shutdown after calling intel_display_driver_suspend_access() no threads are allowed to modeset (as the HW got disabled and should stay in this state). v2: Call intel_display_driver_suspend_access()/resume_access() only for HAS_DISPLAY(). (CI) v3: (Jouni) - Add commit log comments explaining how the permission of modeset changes during HW init/deinit wrt. to the current and other user processes. Link: https://patchwork.freedesktop.org/patch/msgid/20240104132335.2766434-1-imre.deak@intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com>
2023-12-22drm/i915/display: Ignore only psr specific part of vsc sdpJouni Högander
Pipe config check is currently ignoring vsc sdp changes completely if psr is enabled. We want to ignore only PSR part of it as there might be changes in colorimetry data. Also read back vsc_sdp when psr is used. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-6-jouni.hogander@intel.com
2023-12-20Merge tag 'drm-intel-next-2023-12-18' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next - Drop pointless null checks and fix a scaler bug (Ville) - Meteor Lake display fixes and clean-ups (RK, Jani, Andrzej, Mika, Imre) - Clean-up around flip done IRQ (Ville) - Fix eDP Meteor Lake bug (Jani) - Bigjoiner fixes (Ankit, Ville) - Cdclk/voltage_level cleanups and fixes (Ville) - DMC event stuff (Ville) - Remove dead code around intel_atomic_helper->free_list (Jouni) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZYB5XBRdWWgWoMKc@intel.com
2023-12-18drm/i915/display: Remove dead code around intel_atomic_helper->free_listJouni Högander
After switching to directly using dma_fence instead of i915_sw_fence we have left some dead code around intel_atomic_helper->free_list. Remove that dead code. v2: Remove intel_atomic_state->freed as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231114134141.2527694-1-jouni.hogander@intel.com
2023-12-13drm/i915: Reject async flips with bigjoinerVille Syrjälä
Currently async flips are busted when bigjoiner is in use. As a short term fix simply reject async flips in that case. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9769 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211081134.2698-1-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2023-12-13drm/i915/display: Get bigjoiner config before dsc config during readoutAnkit Nautiyal
Currently we get bigjoiner config after the dsc get config, during HW readout. Since dsc_get_config now uses bigjoiner flags/pipes to compute DSC PPS parameter pic_width, this results in a state mismatch when Bigjoiner and DSC are used together. So call get bigjoiner config before calling dsc get config function. Fixes: 8b70b5691704 ("drm/i915/vdsc: Fill the intel_dsc_get_pps_config function") Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231122064627.905828-1-ankit.k.nautiyal@intel.com
2023-12-12Backmerge tag 'v6.7-rc5' into drm-nextDave Airlie
Linux 6.7-rc5 Alex requested this for some amdkfd work relying on the symbols exports. Signed-off-by: Dave Airlie <airlied@redhat.com>
2023-12-08Merge tag 'drm-misc-fixes-2023-12-07' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes drm-misc-fixes for v6.7-rc5: - Document nouveau's GSP-RM. - Flush vmm harder on nouveau tu102. - Panfrost fix for imported dma-buf objects, and device frequency. - Kconfig Build fix for tc358768. - Call end_fb_access after atomic commit. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/05a26dc0-8cf1-4b1f-abb6-3bf471fbfc99@linux.intel.com
2023-12-06drm/atomic-helpers: Invoke end_fb_access while owning plane stateThomas Zimmermann
Invoke drm_plane_helper_funcs.end_fb_access before drm_atomic_helper_commit_hw_done(). The latter function hands over ownership of the plane state to the following commit, which might free it. Releasing resources in end_fb_access then operates on undefined state. This bug has been observed with non-blocking commits when they are being queued up quickly. Here is an example stack trace from the bug report. The plane state has been free'd already, so the pages for drm_gem_fb_vunmap() are gone. Unable to handle kernel paging request at virtual address 0000000100000049 [...] drm_gem_fb_vunmap+0x18/0x74 drm_gem_end_shadow_fb_access+0x1c/0x2c drm_atomic_helper_cleanup_planes+0x58/0xd8 drm_atomic_helper_commit_tail+0x90/0xa0 commit_tail+0x15c/0x188 commit_work+0x14/0x20 Fix this by running end_fb_access immediately after updating all planes in drm_atomic_helper_commit_planes(). The existing clean-up helper drm_atomic_helper_cleanup_planes() now only handles cleanup_fb. For aborted commits, roll back from drm_atomic_helper_prepare_planes() in the new helper drm_atomic_helper_unprepare_planes(). This case is different from regular cleanup, as we have to release the new state; regular cleanup releases the old state. The new helper also invokes cleanup_fb for all planes. The changes mostly involve DRM's atomic helpers. Only two drivers, i915 and nouveau, implement their own commit function. Update them to invoke drm_atomic_helper_unprepare_planes(). Drivers with custom commit_tail function do not require changes. v4: * fix documentation (kernel test robot) v3: * add drm_atomic_helper_unprepare_planes() for rolling back * use correct state for end_fb_access v2: * fix test in drm_atomic_helper_cleanup_planes() Reported-by: Alyssa Ross <hi@alyssa.is> Closes: https://lore.kernel.org/dri-devel/87leazm0ya.fsf@alyssa.is/ Suggested-by: Daniel Vetter <daniel@ffwll.ch> Fixes: 94d879eaf7fb ("drm/atomic-helper: Add {begin,end}_fb_access to plane helpers") Tested-by: Alyssa Ross <hi@alyssa.is> Reviewed-by: Alyssa Ross <hi@alyssa.is> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Cc: <stable@vger.kernel.org> # v6.2+ Link: https://patchwork.freedesktop.org/patch/msgid/20231204083247.22006-1-tzimmermann@suse.de
2023-12-05drm/i915: Skip some timing checks on BXT/GLK DSI transcodersVille Syrjälä
Apparently some BXT/GLK systems have DSI panels whose timings don't agree with the normal cpu transcoder hblank>=32 limitation. This is perhaps fine as there are no specific hblank/etc. limits listed for the BXT/GLK DSI transcoders. Move those checks out from the global intel_mode_valid() into into connector specific .mode_valid() hooks, skipping BXT/GLK DSI connectors. We'll leave the basic [hv]display/[hv]total checks in intel_mode_valid() as those seem like sensible upper limits regardless of the transcoder used. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9720 Fixes: 8f4b1068e7fc ("drm/i915: Check some transcoder timing minimum limits") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231127145028.4899-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit e0ef2daa8ca8ce4dbc2fd0959e383b753a87fd7d) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-12-01drm/i915: add bool type checks in PIPE_CONF_CHECK_*Jani Nikula
Avoid bool/int mismatches in state checker macros. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231129173317.1192269-2-jani.nikula@intel.com
2023-12-01drm/i915: use PIPE_CONF_CHECK_BOOL() for bool membersJani Nikula
Don't treat bools as integers. v2: Rebase Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231129173317.1192269-1-jani.nikula@intel.com
2023-12-01drm/i915: Check pipe active state in {planes,vrr}_{enabling,disabling}()Ville Syrjälä
{planes,vrr}_{enabling,disabling}() are supposed to indicate whether the specific hardware feature is supposed to be enabling or disabling. That can only makes sense if the pipe is active overall. So check for that before we go poking at the hardware. I think we're semi-safe currently on due to: - intel_pre_plane_update() doesn't get called when the pipe was not-active prior to the commit, but this is actually a bug. This saves vrr_disabling(), and vrr_enabling() is called from deeper down where we have already checked hw.active. - active_planes mirrors the crtc's hw.active Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-2-ville.syrjala@linux.intel.com (cherry picked from commit bc53c4d56eb24dbe56cd2c66ef4e9fc9393b1533) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-11-29drm/i915: Clean up some DISPLAY_VER checksVille Syrjälä
Use the >= and < operators for the DISPLAY_VER checks everywhere. This is what most of the code does, but especially recently random pieces of code have started doing this differently for no good reason. Conversion done with the following cocci: @find@ expression i915; constant ver; @@ ( DISPLAY_VER(i915) <= ver | DISPLAY_VER(i915) > ver ) @script:python inc@ old_ver << find.ver; new_ver; @@ coccinelle.new_ver = str(int(old_ver) + 1) @@ expression find.i915; constant find.ver; identifier inc.new_ver; @@ ( - DISPLAY_VER(i915) <= ver + DISPLAY_VER(i915) < new_ver | - DISPLAY_VER(i915) > ver + DISPLAY_VER(i915) >= new_ver ) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231127145028.4899-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-11-29drm/i915: Skip some timing checks on BXT/GLK DSI transcodersVille Syrjälä
Apparently some BXT/GLK systems have DSI panels whose timings don't agree with the normal cpu transcoder hblank>=32 limitation. This is perhaps fine as there are no specific hblank/etc. limits listed for the BXT/GLK DSI transcoders. Move those checks out from the global intel_mode_valid() into into connector specific .mode_valid() hooks, skipping BXT/GLK DSI connectors. We'll leave the basic [hv]display/[hv]total checks in intel_mode_valid() as those seem like sensible upper limits regardless of the transcoder used. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9720 Fixes: 8f4b1068e7fc ("drm/i915: Check some transcoder timing minimum limits") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231127145028.4899-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-11-29drm/i915: Call intel_pre_plane_updates() also for pipes getting enabledVille Syrjälä
We used to call intel_pre_plane_updates() for any pipe going through a modeset whether the pipe was previously enabled or not. This in fact needed to apply all the necessary clock gating workarounds/etc. Restore the correct behaviour. Fixes: 39919997322f ("drm/i915: Disable all planes before modesetting any pipes") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-3-ville.syrjala@linux.intel.com (cherry picked from commit e0d5ce11ed0a21bb2bf328ad82fd261783c7ad88) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-11-23drm/i915/display: Separate xe and i915 common dpt code into own fileJuha-Pekka Heikkila
Here created intel_dpt_common.c to hold intel_dpt_configure which is needed for both xe and i915. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116150225.204233-1-juhapekka.heikkila@gmail.com
2023-11-23drm/i915: Implement audio fastsetVille Syrjälä
There's no real reason why we'd need a full modeset for audio changes. So let's allow audio to be toggled during fastset. In case the ELD changes while has_audio isn't changing state we force both audio disable and enable so the new ELD gets propagated to the audio driver. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-12-ville.syrjala@linux.intel.com
2023-11-23drm/i915: Push audio_{enable,disable}() to the pre/post pane update stageVille Syrjälä
Relocate the audio enable/disable from the full modeset hooks into the common pre/post plane update stage of the commit. Audio fastset is within easy reach now. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-11-ville.syrjala@linux.intel.com
2023-11-23drm/i915: Hoist the encoder->audio_{enable,disable}() calls higher upVille Syrjälä
Push the encoder->audio_{enable,disable}() calls out from the encoder->{enable,disable}() hooks. Moving towards audio fastset. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-10-ville.syrjala@linux.intel.com
2023-11-23drm/i915: Polish some RMWsVille Syrjälä
Doing the if-else around RMWs is kinda silly. Just set/clear the apporiate bits with a single RMW. Also unify the coding style a bit icl_wa_cursorclkgating() while at it. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-4-ville.syrjala@linux.intel.com
2023-11-23drm/i915: Call intel_pre_plane_updates() also for pipes getting enabledVille Syrjälä
We used to call intel_pre_plane_updates() for any pipe going through a modeset whether the pipe was previously enabled or not. This in fact needed to apply all the necessary clock gating workarounds/etc. Restore the correct behaviour. Fixes: 39919997322f ("drm/i915: Disable all planes before modesetting any pipes") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-3-ville.syrjala@linux.intel.com
2023-11-23drm/i915: Check pipe active state in {planes,vrr}_{enabling,disabling}()Ville Syrjälä
{planes,vrr}_{enabling,disabling}() are supposed to indicate whether the specific hardware feature is supposed to be enabling or disabling. That can only makes sense if the pipe is active overall. So check for that before we go poking at the hardware. I think we're semi-safe currently on due to: - intel_pre_plane_update() doesn't get called when the pipe was not-active prior to the commit, but this is actually a bug. This saves vrr_disabling(), and vrr_enabling() is called from deeper down where we have already checked hw.active. - active_planes mirrors the crtc's hw.active Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-2-ville.syrjala@linux.intel.com
2023-11-21drm/i915/dp: Reuse intel_dp_{max,effective}_data_rate in ↵Imre Deak
intel_link_compute_m_n() Reuse intel_dp_max_data_rate() and intel_dp_effective_data_rate() in intel_link_compute_m_n(), instead of open-coding the equivalent. Note the kbit/sec -> kByte/sec unit change in the M/N values, but this not reducing the precision, as the link rate value is based anyway on a less precise 10 kbit/sec value. Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-12-imre.deak@intel.com
2023-11-21drm/i915/dp: Fix UHBR link M/N valuesImre Deak
The link M/N ratio is the data rate / link symbol clock rate, fix things up accordingly. On DP 1.4 this ratio was correct as the link symbol clock rate in that case matched the link data rate (in bytes/sec units, the symbol size being 8 bits), however it wasn't correct for UHBR rates where the symbol size is 32 bits. Kudos to Arun noticing in Bspec the incorrect use of link data rate in the ratio's N value. Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-7-imre.deak@intel.com
2023-11-21drm/i915/dp: Account for channel coding efficiency on UHBR linksImre Deak
Apply the correct BW allocation overhead and channel coding efficiency on UHBR link rates, similarly to DP1.4 link rates. Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-6-imre.deak@intel.com
2023-11-21drm/i915/dp: Replace intel_dp_is_uhbr_rate() with drm_dp_is_uhbr_rate()Imre Deak
Replace intel_dp_is_uhbr_rate() with the recently added drm_dp_is_uhbr_rate(). Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-5-imre.deak@intel.com
2023-11-17drm/i915: move *_crtc_clock_get() to intel_dpll.cJani Nikula
Considering what the functions do, intel_dpll.c is a more suitable location, and lets us make some functions static while at it. This also means intel_display.c no longer does any DPIO access. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231114104534.4180144-1-jani.nikula@intel.com
2023-11-14drm/i915/display: Consider fractional vdsc bpp while computing m_n valuesAnkit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. v1: Replace the computation of 'data_clock' with 'data_clock = DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng). v2: Rebase and pass bits_per_pixel in U6.4 format. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn> Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-4-ankit.k.nautiyal@intel.com
2023-11-14drm/i915/display: Store compressed bpp in U6.4 formatAnkit Nautiyal
DSC parameter bits_per_pixel is stored in U6.4 format. The 4 bits represent the fractional part of the bpp. Currently we use compressed_bpp member of dsc structure to store only the integral part of the bits_per_pixel. To store the full bits_per_pixel along with the fractional part, compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply right shifting the member compressed_bpp by 4. v2: -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing with compressed bpp. (Suraj) -Fix comment styling. (Suraj) v3: -Add separate file for 6.4 fixed point helper(Jani, Nikula) -Add comment for magic values(Suraj) v4: -Fix checkpatch warnings caused by renaming(Suraj) v5: -Rebase. -Use existing helpers for conversion of bpp_int to bpp_x16 and vice versa. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn> Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-3-ankit.k.nautiyal@intel.com
2023-11-08drm/i915: Do plane/etc. updates more atomically across pipesVille Syrjälä
Perform all the intel_pre_update_crtc() stuff for all pipes first, and only then do the intel_update_crtc() vblank evasion stuff for every pipe back to back. This should make it more likely that the plane updates from multiple pipes happen on the same frame (assuming the pipes are running in sync, eg. due to bigjoiner or port sync). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230907122541.32261-4-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2023-11-08drm/i915: Split intel_update_crtc() into two partsVille Syrjälä
Split intel_update_crtc() into two parts such that the first part performs all the non-vblank evasion preparatory stuff, and the second part just does the vblank evasion stuff. For now we just call these back to back so that there is no funcitonal change. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230907122541.32261-3-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2023-11-08drm/i915: Drop redundant !modeset checkVille Syrjälä
Since commit 7de5b6b54630 ("drm/i915: Don't flag both full modeset and fastset at the same time") intel_crtc_needs_fastset() and intel_crtc_needs_modeset() have been mutually exclusive. Drop the redundant check. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230907122541.32261-2-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2023-11-08drm/i915/dp_mst: Improve BW sharing between MST streamsImre Deak
At the moment modesetting a stream CRTC will fail if the stream's BW along with the current BW of all the other streams on the same MST link is above the total BW of the MST link. Make the BW sharing more dynamic by trying to reduce the link bpp of one or more streams on the MST link in this case. When selecting a stream to reduce the BW for, take into account which link segment in the MST topology ran out of BW and which streams go through this link segment. For instance with A,B,C streams in the same MST topology A and B may share the BW of a link segment downstream of a branch device, stream C not downstream of the branch device, hence not affecting this BW. If this link segment's BW runs out one or both of stream A/B's BW will be reduced until their total BW is within limits. While reducing the link bpp for a given stream DSC may need to be enabled for it, which requires FEC on the whole MST link. Check for this condition and recompute the state for all streams taking the FEC overhead into account (on 8b/10b links). v2: - Rebase on s/min_bpp_pipes/min_bpp_reached_pipes/ change. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231030155843.2251023-29-imre.deak@intel.com
2023-11-08drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires itImre Deak
Enabling / disabling DSC decompression in the branch device downstream of the source may reset the whole branch device. To avoid this while the streams are still active, force a modeset on all CRTC/ports connected to this branch device. v2: - Check the CRTC state for each connector in the topology, instead of the CRTC being checked for a modeset requirement. (Ville) - Add DocBook for the new function. v3: - Rebased on a change not to use intel_modeset_pipes_in_mask_early(). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1) Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231107001505.3370108-8-imre.deak@intel.com
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 20:01:00 +0000