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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c
AgeCommit message (Expand)Author
2019-09-10drm/i915: Enhance cdclk sanitizationMatt Roper
2019-09-10drm/i915: Add calc_voltage_level display vfuncMatt Roper
2019-09-10drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclkMatt Roper
2019-09-10drm/i915: Kill cnl_sanitize_cdclk()Matt Roper
2019-09-10drm/i915: Combine bxt_set_cdclk and cnl_set_cdclkMatt Roper
2019-09-10drm/i915: Use literal representation of cdclk tablesMatt Roper
2019-09-10drm/i915: Consolidate bxt/cnl/icl cdclk readoutMatt Roper
2019-09-06drm/i915/tgl: Use refclk/2 as bypass frequencyMatt Roper
2019-08-30drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+Matt Roper
2019-08-30drm/i915: Allow /2 CD2X divider on gen11+Matt Roper
2019-08-23drm/i915: Use enum pipe instead of crtc index to track active pipesVille Syrjälä
2019-08-16drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula
2019-07-18drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHVVille Syrjälä
2019-07-11drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()Ville Syrjälä
2019-06-26drm/i915/ehl: Add voltage level requirement tableJosé Roberto de Souza
2019-06-26drm/i915/ehl: Remove unsupported cd clocksJosé Roberto de Souza
2019-06-26drm/i915/icl: Add new supported CD clocksJosé Roberto de Souza
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula