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path: root/drivers/gpu/drm/amd/powerplay
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2018-05-15drm/amd/powerplay: add gfx off control functionHuang Rui
gfx_off_control is used to be called for sending enabling/disabling gfxoff message. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amdgpu: move PP_FEATURE_MASK to amd_shared headerHuang Rui
It will be used not only for powerplay but also on amdgpu part in future patches. So move it into amd_shared header file. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/powerplay: send CGPG smc message if PG is enabled for ravenHuang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/powerplay: add registry key to disable ACGKenneth Feng
For the dummy ACG fuses,need to disable ACG, otherwise corruption will be caused. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/powerplay: header file interface to SMU updateKenneth Feng
update vega12 smu interface. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Fix NULL point check error in smu_set_watermarks_for_clocks_rangesRex Zhu
It is caused by 'commit d6c9a7dc86cd ("drm/amd/pp: Move common code to smu_helper.c")' Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Fix bug voltage can't be OD separately on VIRex Zhu
Make sure to update the MCLK and SCLK flags when setting the VDDC flags due to dependencies. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Remove dead interfaceRex Zhu
Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amdgpu: Reserved vram for smu to save debug info.Rex Zhu
v2: check reserved vram size before allocate. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Adding a function to store cc6 data in SMU10Mikita Lipski
Filling the smu10_store_cc6_data based on the implementation of Windows Powerplay. There is an uncertainty with one of the parameters passed to the function pstate_switch_disable - is not a part of smu10 private data structure. So in the function its just ignored. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Adding set_watermarks_for_clocks_ranges for SMU10Mikita Lipski
The function is never implemented for raven on linux. It follows similair implementation as on windows. SMU still needs to notify SMC and copy WM table, which is added here. But on other Asics such as Vega this step is not implemented. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Move common code to smu_helper.cRex Zhu
Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Clear smu response register before send smu messageRex Zhu
smu firmware do not update response register immediately under some delay tasks, we may read out the original value. so need to clear the register before send smu message. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Remove struct pp_gpu_powerRex Zhu
Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, User need to set start time and end time, firmware can calculate the average vddc/vddci/max power. but the type of return values is not unified. For Vi, return type is uint. For vega, return type is float. so this struct can't be suitable for all asics. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Refine get_gpu_power for VIRex Zhu
pkgpwr is the average gpu power of 100ms. it is calculated by firmware in real time. 1. we can send smu message PPSMC_MSG_GetCurrPkgPwr to read currentpkgpwr directly. 2. On Fiji/tonga/bonaire/hawwii, without PPSMC_MSG_GetCurrPkgPwr support. Send PPSMC_MSG_PmStatusLogStart/Sample to let smu write currentpkgpwr to ixSMU_PM_STATUS_94. driver can read pkgpwr from ixSMU_PM_STATUS_94. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15Revert "drm/amd/powerply: fix power reading on Fiji"Rex Zhu
we don't have limit of [50ms, 4sec] sampling period. smu calculate average gpu power in real time. we can read average gpu power through smu message or read special register. This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amdgpu/powerplay: rename smu7_upload_mc_firmwareAlex Deucher
It doesn't actually upload any firmware is just checks the version. The actual upload happens in the gmc modules. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amdgpu/powerplay: fix smu7_get_memory_type for fijiAlex Deucher
Fiji uses a different register than other smu7 asics, but we already have this info in the base driver so just use that. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Remove useless smu7 running state checkRex Zhu
Only check smc running state before start smu. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Remove dead function in smu7_smumgr.cRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/powerplay: initialzie the dpm intial enabled stateKenneth Feng
To expose the right dpm levels to the sysfs Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/powerplay: Get more than 8 level gfxclk statesKenneth Feng
To apply on Vega12 for more than 8 gfx dpm levels Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15amd/powerplay: implement the vega12_force_clock_level interfaceKenneth Feng
pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force gfxclk/uclk dpm level for Vega12 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Remove unnecessary forward declarationRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Move same macro definitions to hwmgr.hRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: fix the wrong readout engine clock in deep sleepEvan Quan
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: use soc15 common macros instead of vega10 specificEvan Quan
pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common macros defined in soc15_common.h. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15drm/amd/pp: Refine pp_atomfwctrl_get_vbios_bootup_valuesRex Zhu
In order to share pp_atomfwctrl_get_vbios_bootup_values on asics with different BIOS_CLKID. Not call function pp_atomfwctrl_get_clk_information_by_clkid in pp_atomfwctrl_get_vbios_bootup_values. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amdgpu: remove duplicate cg/pg wrapper functionsRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König<christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Not call cgs interface to get display infoRex Zhu
DC/Non DC all will update display configuration when the display state changed No need to get display info through cgs interface Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Use atombios api directly in powerplay (v2)Rex Zhu
In order to remove the cgs wrapper functions for atombios api. v2: squash in whitespace cleanup (Alex) Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Use gfx rlc funcs directly in powerplayRex Zhu
In order to remove cgs interfaces: cgs_enter_safe_mode cgs_lock_grbm_idx Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Fix spelling mistake: "suppported" -> "supported"Colin Ian King
Trivial fix to spelling mistake in pr_warn warning message text Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amdgpu: Use dpm_enabled as dpm state flagRex Zhu
driver will set dpm_enabled to true only when module parameter amdgpu_dpm not equal to 0 and smu hw initialize successfully. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Use release_firmware directly in powerplayRex Zhu
Use kernel api directly so we can deprecate the cgs interface. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Save vf state in pp contextRex Zhu
Store vf state in pp_context so we can deprecate the cgs interface. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Lock pm_funcs when set pp tableRex Zhu
unlock mutex until set pp table completely to avoid conflict if other pp functions were called simultaneously. use hwmgr_handle_task instand of pp_dpm_dispatch_tasks. It is not make sense that call pp_functions in ip_functions. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Add hwmgr_sw_init/fini functioinsRex Zhu
Clean up pp ip functions Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/pp: Remove useless fw load error handler on PolarisRex Zhu
Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-03drm/amd/powerply: fix power reading on FijiEric Huang
Power value is wrong reported by customer. It is a regression by commit a7c7bc4c0c47eaac77b8fa92f0672032df7f4254 Author: Rex Zhu <Rex.Zhu@amd.com> Date: Mon Mar 27 15:32:59 2017 +0800 drm/amd/powerplay: reduce sample period time for power readings. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> The theoretical sampling period is from 50ms to 4sec, original 2sec is long but correct, and 20ms is too short. change it to more reasonable 200ms. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-03drm/amd/powerplay: Enable ACG SS featureKenneth Feng
Port the atomfirmware.h and populates the updated pptable to SMU.With the new parameters in the new pptable, the ACG SS feature is enabled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-03drm/amd/pp: Clean header file in vega12_smumgr.cRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-03drm/amd/pp: Remove Dead functions on Vega12Rex Zhu
Remove Vega12 DIDT config functions. Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-03drm/amd/pp: silence a static checker warningDan Carpenter
This has a static checker warning because "frev" and "crev" can be uninitialized if "info" is NULL. I just changed the order of the checks so that we check "info" first. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-23drm/amd/pp: clean header file hwmgr.hRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-23drm/amd/pp: use mlck_table.count for array loop index limitColin Ian King
v2: use temporaries to trivially reduces object size. The for-loops process data in the mclk_table but use slck_table.count as the loop index limit. I believe these are cut-n-paste errors from the previous almost identical loops as indicated by static analysis. Fix these. Detected by CoverityScan, CID#1466001 ("Copy-paste error") Fixes: 5d97cf39ff24 ("drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.") Fixes: 5e4d4fbea557 ("drm/amd/pp: Implement edit_dpm_table on smu7") Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-22drm/amd/pp: Add new asic support in pp_psm.cRex Zhu
In new asics(vega12), no power state management in driver, So no need to implement related callback functions. and add some ps checks in pp_psm.c Revert "drm/amd/powerplay: add new pp_psm infrastructure for vega12 (v2)" This reverts commit 7d1a63f3aa331b853e41f92d0e7890ed31de8c13. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-22drm/amd/pp: Clean up powerplay code on Vega12Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-22drm/amd/pp: Add smu irq handlers for legacy asicsRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-22drm/amd/pp: Fix set wrong temperature range on smu7Rex Zhu
Fix the issue thermal irq was always triggered as GPU under temperature range detected The low temp in default thermal policy was set to -273. so need to use int type for the low temp. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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