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path: root/drivers/gpu/drm/amd/include/asic_reg
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2016-09-19drm/amdgpu: implement raster configuration for gfx v6Huang Rui
This patch is to implement the raster configuration and harvested configuration of gfx v6. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31drm/amdgpu: add si implementation v10Ken Wang
v5: rebase fixes v6: add mgcg arrays v7: rebase fixes v8: rebase fixes v9: add get_disabled_bios(), make get_xclk static v10: fix oland and hainan asic specific handle at si_program_aspm Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31drm/amdgpu: add DMA implementation for si v8Ken Wang
v4: rebase fixes v5: use the generic nop fill v6: rebase fixes v7: rebase fixes copy count fixes from Jonathan general cleanup add fill buffer implementation v8: adapt write_pte and copy_pte to latest changes Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31drm/amdgpu: add display controller implementation for si v10Ken Wang
v4: rebase fixups v5: more fixes based on dce8 code v6: squash in dmif offset fix v7: rebase fixups v8: rebase fixups, drop some debugging remnants v9: fix BE build v10: include Marek's tiling fixes, add support for page_flip_target, set MASTER_UDPATE_MODE=0, fix cursor Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31drm/amdgpu: add si header files v4Ken Wang
v4: drop unused DCE6 macro Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-24drm/amdgpu: switch UVD code to use UVD_NO_OP for paddingAlex Deucher
Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-24drm/amdgpu: add support for UVD_NO_OP registerAlex Deucher
Writes to this register are the preferred way to do NOPs. Bump the driver version as well. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-29drm/amdgpu: add new definition in bif headerHuang Rui
This patch adds new definition in bif header, and will be used on iceland HW powertune part. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-29drm/amdgpu: implement UVD VM mode for Stoney v2Christian König
Starting with Stoney we support running UVD in VM mode as well. v2: rebased, only enable on Polaris for now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd/powerplay: add shared definitions for di/dt feature.Rex Zhu
v1: delete some comflict definitions between polaris and fiji. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: remove gfx8 registers that vary between asicsKen Wang
those register mask definitions are different in polaris compare to former gfx 8 gpus, so remove them from misusing. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu/gfx80: Add QUICK_PG bit to GFX header and use it.Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3DFlora Cui
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd: add DCE 11.2 register headersAlex Deucher
Add register headers for DCE (Display and Composition Engine) 11.2. Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: handle more than 10 UVD sessions (v2)Arindam Nath
Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-17drm/amdgpu/gfx7: add MTYPE definitionFlora Cui
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-12drm/amd/include: Update dce 8 headers for dalHarry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amd: add dce8 enum register headerAlex Deucher
This adds the DCE8 enum header. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.hyanyang1
Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by new powerplay code for tonga and fiji. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-02drm/amd: add new gfx8 register definitions for EDCAlex Deucher
EDC is a RAS feature for on chip memory. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-28drm/amdgpu: add GFX 8.1 register headersAlex Deucher
Minor differences compared to GFX 8.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: Add Fiji smu 7.1.3 headers (v2)David Zhang
v2: agd5f: prepare for release Signed-off-by: David Zhang <david1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-03drm/amdgpu: add VCE 3.0 register headersAlex Deucher
These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add VCE 2.0 register headersAlex Deucher
These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add UVD 6.0 register headersAlex Deucher
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add UVD 5.0 register headersAlex Deucher
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add UVD 4.2 register headersAlex Deucher
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add SMU 8.0 register headersAlex Deucher
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add SMU 7.1.2 register headersAlex Deucher
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add SMU 7.1.1 register headersAlex Deucher
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add SMU 7.1.0 register headersAlex Deucher
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add SMU 7.0.1 register headersAlex Deucher
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add SMU 7.0.0 register headersAlex Deucher
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add OSS 3.0.1 register headersAlex Deucher
These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add OSS 3.0 register headersAlex Deucher
These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add OSS 2.4 register headersAlex Deucher
These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add OSS 2.0 register headersAlex Deucher
These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GMC 8.2 register headersAlex Deucher
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GMC 8.1 register headersAlex Deucher
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GMC 7.1 register headersAlex Deucher
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GMC 7.0 register headersAlex Deucher
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GCA 8.0 register headersAlex Deucher
These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GCA 7.2 register headersAlex Deucher
These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add GCA 7.0 register headersAlex Deucher
These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add DCE 11.0 register headersAlex Deucher
These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add DCE 10.0 register headersAlex Deucher
These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add DCE 8.0 register headersAlex Deucher
These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add BIF 5.1 register headersAlex Deucher
These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add BIF 5.0 register headersAlex Deucher
These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add BIF 4.1 register headersAlex Deucher
These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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