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path: root/drivers/gpu/drm/amd/display/dc/link
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2023-08-30drm/amd/display: Add DCN35 DIOQingqing Zhuo
[Why & How] Add DIO handling for DCN35. Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Add DPIA Link Encoder Assignment FixMustapha Ghaddar
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design. Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Refactor edp power controlIan Chen
[Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Handle Replay related hpd irqBhawanpreet Lakha
Handle replay related hpd irqs Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-15drm/amd/display: implement pipe type definition and adding accessorsWenjing Liu
[why] There is a lack of encapsulation of pipe connection representation in pipe context. This has caused many challenging bugs and coding errors with repeated logic to identify the same pipe type. [how] Formally define pipe types and provide getters to identify a pipe type and find a pipe based on specific requirements. Update existing logic in non dcn specific files and dcn32 and future versions to use the new accessors. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-15drm/amd/display: Support Compliance Test Pattern Generation with DP2 RetimerMichael Strauss
[WHY] Certain retimer requires workarounds in order to correctly output test patterns. [HOW] Add vendor-specific aux sequences to program retimer's TX and pattern generator when specific compliance test patterns are requested by sink. Note: SQ128 w/a in DPMF mode only works in one flip orientation currently Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: fix a regression in blank pixel data caused by coding mistakeWenjing Liu
[why] There was unfortunately a coding mistake. It gets caught with an ultrawide monitor that requires ODM 4:1 combine. We are blanking or unblanking pixel data we are supposed to enumerate through all ODM pipes and program DPG for each of those pipes. However the coding mistake causes us to program only the first and last ODM pipes. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Read replay data from sinkBhawanpreet Lakha
Read DP_SINK_PR_PIXEL_DEVIATION_PER_LINE and DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Add Functions to enable Freesync Panel ReplayBhawanpreet Lakha
Add various functions for replay, such as construct, destroy, enable get_state, and copy_setting etc. These functions communicate with the firmware to setup and enable panel replay Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Add symclk enable/disable during stream enable/disableTaimur Hassan
[Why & How] Using dig_stream_mapper, program symclk_en and symclk_fe_src_sel when enabling or disabling the corresponding stream. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Remove check for default eDP panel_modeTaimur Hassan
[Why] DPCD read is skipped first time after driver initialization. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Add new sequence for 4-lane HBR3 on vendor specific retimersOvidiu Bunea
[Why] In some vendor specific retimer setups for downstream 4-lane HBR3 configuration, the sink will show severe corruption (horizontal shifting) and intermittent blanking. [How] Add new retimer programming sequence before clock recovery when 4 lanes are active. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Update DPG test pattern programmingWenjing Liu
[Why] Last ODM slice could be slightly larger than other slice because it can be including the residual. [How] Update DPG pattern programming sequence to use a different width for last odm slice. Reviewed-by: Chris Park <chris.park@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Add VESA SCR case for default aux backlightIswara Nagulendran
[How & Why] When determining default aux backlight level, read from DPCD address 0x734 for VESA SCR on OLED. Reviewed-by: Felipe Clark <felipe.clark@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Iswara Nagulendran <iswara.nagulendran@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Fix ASIC check in aux timeout workaroundTaimur Hassan
[Why] Aux write was meant to be ASIC specific, and is causing compliance failures on newer parts. [How] Make workaround specific to single ASIC. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Add link encoding to timing BW calculation parametersGeorge Shen
[Why] There certain cases where the timing BW is dependent on the type of link encoding in use. Thus to calculate the correct BW required for a given timing, the link encoding should be added as a parameter. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: refine to decide the verified link settingZhikai Zhai
[WHY] We return false by default when link training fail at link loss. It will cause we get a fail verified link caps directly. [HOW] Record the highest verified link caps. Use the recorded value as the verified link caps if it is not successful in the last attempt to avoid to use the lowest link setting. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Fix DP2 link training failure with RCODaniel Miess
[Why] When RCO is enabled for symclk32_le we get failures during DP2 link traing compliance tests. [How] Break out symclk32_le RCO into a separate function that is called for hpo when link is enabled/disabled. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Cache backlight_millinits in link structure and setting ↵Nicholas Susanto
brightness accordingly [Why] Need to save the cached backlight level so that display lights up using appropriate brightness level instead of the default brightness when waking up from s0i3. [How] Adding a backlight level cache in link structure. Also instead on calling set_default_brightness_aux, check if cached values exists. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Re-add aux intercept disable delay generically for 2+ LTTPRsMichael Strauss
[WHY] Issue not display generic, required for multiple 2+ LTTPR link configurations. [HOW] Revert monitor patch change and remove delay for single LTTPR case Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Setup stream encoder before link enable for TMDSJinZe Xu
[Why] HDMI spec requires TMDS clock to be not more than 340MHz. Stream encoder ensure this requirement but driver enable stream encoder later than PHY. So PHY will output full speed TMDS clock first. [How] Enable stream encoder first in TMDS case. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: JinZe Xu <jinze.xu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-30drm/amd/display: Work around bad DPCD state on link lossIlya Bakoulin
[Why] This display doesn't properly indicate link loss through DPCD bits such as CR_DONE / CHANNEL_EQ_DONE / SYMBOL_LOCKED / INTERLANE_ALIGN_DONE, which all remain set. In addition, DPCD200Eh doesn't match the value of DPCD204h in all cases. For these reasons, we can miss re-training the link, since we don't properly detect link loss with this display. [Why] Add display-specific workaround to read DPCD204h, so that we can detect link loss based on 128b132b-specific status bits in this register. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-23drm/amd/display: Fix 128b132b link loss handlingIlya Bakoulin
[Why] We don't check 128b132b-specific bits in LANE_ALIGN_STATUS_UPDATED DPCD registers when parsing link loss status, which can cause us to miss a link loss notification from some sinks. [How] Add a 128b132b-specific status bit check. Cc: stable@vger.kernel.org # 6.3+ Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-15drm/amd/display: limit DPIA link rate to HBR3Peichen Huang
[Why] DPIA doesn't support UHBR, driver should not enable UHBR for dp tunneling [How] limit DPIA link rate to HBR3 Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Peichen Huang <peichen.huang@amd.com> Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Add control flag to dc_stream_state to skip eDP BL off/link offMax Tseng
Add control flag to dc_stream_state to skip eDP BL off/link off. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Max Tseng <max.tseng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: clean up some inconsistent indentingJiapeng Chong
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:2377 link_set_dpms_on() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5376 Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Clean FPGA code in dcQingqing Zhuo
[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: lower dp link training message levelHersen Wu
[Why] some test apps report dp link training waring even dp training pass. there are 4 tries of lt within perform_link_training_with_retries. if lt pass within 4 tries, it will NOT be reated as lt failure. for each try of lt, if lt fails, current driver implementation prints message at warning level. this let people think dp lt does not work properly. [How] for 1st, 2nd and 3rd try of lt, print message at debug level. for the 4th try of lt, print message at warning level. Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Convert connector signal id to stringRodrigo Siqueira
To improve the readability of the of the log, this commit introduces a function that converts the signal type id to a human-readable string. Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: enable dpia validateMustapha Ghaddar
Use dpia_validate_usb4_bw() function Fixes: a8b537605e22 ("drm/amd/display: Add function pointer for validate bw usb4") Reviewed-by: Roman Li <roman.li@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Add w/a to disable DP dual mode on certain portsGeorge Shen
[Why] Certain ports on DCN3.2 configs do not properly populate the BIOS info table flag to indicate DP dual mode is unsupported. [How] Add a workaround to disable DP dual mode on the ports with the missing BIOS info table flag. Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Add logging when DP link training Channel EQ is SuccessfulSrinivasan Shanmugam
Log when Channel Equalization is successful. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Add logging for eDP v1.4 supported sink ratesSrinivasan Shanmugam
Include eDP v1.4 panels supported sink rates in debug output, useful info for knowing optimized link rates Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Jerry Zuo <jerry.zuo@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: DSC passthrough is for DP-HDMI pcon (SST pcon)Srinivasan Shanmugam
if check over DSC passthrough is removed, as this is not for MST use case. It is for DP-HDMI pcon use case. sst pcon is detected as sst not mst. In sst pcon dsc passthrough message will not get below log printed Fixes: 9b035d089086 ("drm/amd/display: Check & log if receiver supports MST, DSC & FEC.") Suggested-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Keep disable aux-i delay as 0Michael Strauss
[WHY] Current Aux-I sequence checks for local_sink which isn't populated on MST links [HOW] Leave disable aux-i delay as 0 for MST cases Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Convert Delaying Aux-I Disable To Monitor PatchMichael Strauss
[WHY] 32ms delay was added to resolve issue with a specific sink, however this same delay also introduces erroneous link training failures with certain sink devices. [HOW] Only apply the 32ms delay for offending devices instead of globally. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: Improvement for handling edp link training failsJingwen Zhu
[Why] The eDP retrain will cause the DPCD 300 to be reset to default. And cause the brightness can't be set correctly. [How] delete the call to edp panel power control in both enable_link_output/disable_link_output entirely and only call edp panel control in enable_link_dp and  disable_link_dp once. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: Apply correct panel mode when reinitializing hardwareMichael Mityushkin
[Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Michael Mityushkin <michael.mityushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: Adding support for VESA SCRIswara Nagulendran
[HOW&WHY] Write DPCD 721 bit 7 to high, and the appropriate luminance level to DPCD 734-736 if bit 4 from DPCD register 734 is high, indicating that the panel luminance control is enabled from the panel side. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: refactor dmub commands into single functionJosip Pavic
[Why & How] Consolidate dmub access to a single interface. This makes it easier to add code in the future that needs to run every time a dmub command is requested (e.g. instrumentation, locking etc). Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: Check & log if receiver supports MST, DSC & FEC.Srinivasan Shanmugam
After reading from receiver via DPCD, check & log if it supports MST, DSC & FEC Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: Unconditionally print when DP sink power state failsSrinivasan Shanmugam
The previous 'commit ca9beb8aac68 ("drm/amd/display: Add logging when setting DP sink power state fails")', it is better to unconditionally print "failed to power up sink", because we are returning DC_ERROR_UNEXPECTED. Fixes: ca9beb8aac68 ("drm/amd/display: Add logging when setting DP sink power state fails") Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-14drm/amd/display: Add logging when DP link training Clock recovery is SuccessfulSrinivasan Shanmugam
Log when Clock recovery is successful, as part of DP link training process. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-14drm/amd/display: Add logging when setting DP sink power state failsSrinivasan Shanmugam
Log if we fail to setup sink power states. Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Add logging for DP link traning Test Pattern SeqeuncesSrinivasan Shanmugam
Add some more logging for DP link traning test pattern seqeunces for better debugging. Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display : Log DP link training downspread infoSrinivasan Shanmugam
Update the existing log with DP LT downspread info: [Downstream devices shall support down spreading of the link clock. The down-spread amplitude shall either be disabled (0.0%) or up to 0.5%, as written by the upstream device to the DOWNSPREAD_CTRL register (DPCD 00107h). The modulation frequency range shall be 30 to 33 kHz] Besides, fix checkpatch warning: CHECK: Alignment should match open parenthesis Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Improve robustness of FIXED_VS link training at DP1 ratesMichael Strauss
[WHY] New sequence for transparent mode DP1.x link training was provided by LTTPR vendor [HOW] Implement new FIXED_VS sequence, increase LT retry count to minimize any potential intermittent lightup failures Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-31drm/amd/display: skip CLEAR_PAYLOAD_ID_TABLE if device mst_en is 0Peichen Huang
[Why] Some dock and mst monitor don't like to receive CLEAR_PAYLOAD_ID_TABLE when mst_en is set to 0. It doesn't make sense to do so in source side, either. [How] Don't send CLEAR_PAYLOAD_ID_TABLE if mst_en is 0 Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-31drm/amd/display: Conditionally enable 6.75 GBps link rateArtem Grishin
[Why] The 6.75 GBps link rate is part of the new eDP specification version 1.5 is going to be supported in the future. Since this standard is very new and there are no existing 6.75 GBps panels on the market yet, we should put a condition in the driver on enabling this feature until we can validate it with real hardware. [How] - Add boolean flag support_eDP1_5 in struct dc_debug_options. - Enable the 6.75 link rate in reduce_link_rate(...) only when the flag is true. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Artem Grishin <Artem.Grishin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-31drm/amd/display: Add support for 6.75 GBps link rateArtem Grishin
[Why] The latest eDP spec version 1.5 defines a new generic link rate of 6.75 Gbps/Lane, which needs to be supported in the driver. [How] Added new element to the dc_link_rate enum Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Artem Grishin <Artem.Grishin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-31 23:01:55 +0000