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path: root/drivers/gpu/drm/amd/display/dc/dsc
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2019-06-22drm/amd/display: Add 170Mpix/sec DSC throughput supportNikola Cornij
[why] It was missing, although defined in DP spec [how] - Add handling of this value to DSC code - Also remove unused file dsc_helpers.c Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Consider DSC target bpp precision when calculating DSC ↵Nikola Cornij
target bpp [why] DSC target bpp precision is a decoder DPCD and an AMD encoder capability. It must be taken into account when calculating target bitrate. [how] Add a DC DSC function that does this calculation. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Implement DSC MST fair share algorithmWenjing Liu
[why] The current policy will always enable DSC to 12 bpp regardless of if the current bandwidth is enough for MST displays. This logic is not optimal because user will get lower quality output if DSC compression is enabled. This change to is to implement a DSC MST bandwidth fair share algorithm so we will dynamically decide if DSC is needed and what quality (target bpp) is needed to fairly destribute the MST bandwidth in one MST topology. This will allow user to see the most optimal image quality with the given bandwidth. [how] We will start with lowest bandwidth possible and run a Max-Min fairness algorithm to fairly distribute the available bandwidth. If there is still remaining bandwidth, we will try to fit the timing without DSC compression. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Make sure DSC slice height is divisible by 2 for 4:2:0 ↵Nikola Cornij
color format [why] DSC spec requires this Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Use 1/8th DSC target bitrate precision for N4:2:2 and 4:2:0 ↵Nikola Cornij
formats [why] On at least some of the devices (e.g. Realtek scaler) we get a black screen if 1/16th precision is used. [how] Work around it by reducing precision to 1/8th for N4:2:2 and 4:2:0 color formats. This is a safe workaround and would have a very mild impact on the quality. The issue is still to be root-caused and fixed correctly. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Remove additional FEC link bandwidth reductionNikola Cornij
[why] This is now done in the original link bandwidth calculation and DSC must not do this anymore. [how] Remove the line of code that should have been removed when transition to correctly applying FEC overhead was made. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: remove target_dpp hack for dscWenjing Liu
Remove dc_dsc hack for MST policy Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: remove legacy DSC functionsWenjing Liu
[why] Clean up some dsc legacy functions that are no longer needed. [how] remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing instead of calc_required_bandwidth_for_timing. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Calculate link bandwidth in a common functionNikola Cornij
[why] Currently link bandwidth is calculated in various places using the same multi-step formula. Doing this in one common place makes sure the same formula will indeed be applied to all link bandwidth calculations. It also makes it possible to apply link-setting-specific adjustments that affect effective link bandwidth. [how] Replace all implementations of link bandwidth calculation with a call to a function. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DSC support for Navi (v2)Harry Wentland
Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>