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path: root/drivers/gpu/drm/amd/display/dc/dcn302
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2021-01-25amdgpu: fix clang build warningArnd Bergmann
clang warns about the -mhard-float command line arguments on architectures that do not support this: clang: error: argument unused during compilation: '-mhard-float' [-Werror,-Wunused-command-line-argument] Move this into the gcc-specific arguments. Fixes: e77165bf7b02 ("drm/amd/display: Add DCN3 blocks to Makefile") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/display: Update dcn30_apply_idle_power_optimizations() codeBhawanpreet Lakha
Update the function for idle optimizations -remove hardcoded size -enable no memory-request case -add cursor copy -update mall eligibility check case Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/display: Dynamic cursor cache size for MALL eligibility checkBhawanpreet Lakha
[Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amdgpu/display: drop DCN support for aarch64Alex Deucher
From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amd/display: Create and Destroy PSR resources for DCN302Joshua Aberback
We need these to support PSR on DCN302 Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amd/display: remove useless else ifTian Tao
Fix the following coccinelle report: drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c:1357:6-8: WARNING: possible condition with no effect (if == else) Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/display: Source minimum HBlank supportAshley Thomas
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/display: add i2c speed arbitration for dc_i2c and hdcp_i2cCharlene Liu
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] slower down the HW i2c speed when used by HW i2c. this request: each acquired_i2c_engine setup the i2c speed needed. and set the I2c engine for HDCP use at release_engine. this covers SW using HW I2c engine and HDCP using HW I2c engine. for dmcu using HW I2c engine, needs add similar logic in dmcufw. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/display: Add DPCS regs for dcn302 link encoderBhawanpreet Lakha
dpcs reg are missing for dcn302 link encoder regs list, so add them. Just like dcn3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: force use sRGB for video TF is sRGB or BT709Jing Zhou
[Why] When mpo enabled, video comes is 709. Desktop use sRGB. So color change easily noticeable especially when switch between mpo/non-mpo. [How] Force use sRGB for video TF is sRGB or BT709. DCN1/DCN2 use predefined type with YUV. DCN3 use distributed points type with YUV. Signed-off-by: Jing Zhou <Jing.Zhou@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amdgpu: Add and use seperate reg headers for dcn302Bhawanpreet Lakha
Currently we are using dcn3 reg headers for dcn302. The offsets are different between the two so they need seperate headers. Add dcn302 header files and use these instead of dcn3 header Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Update panel registerChris Park
[Why] Incorrect panel register settings are applied for power sequence because the register macro is not defined in resource. [How] Implement same register space to future resource files. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-26drm/amd/display: Refactor ABM_MASK_SH_LIST_DCN301 namingRoman Li
[Why] All DCN3x resources share ABM_MASK_SH_LIST_DCN301 definition. The naming is misleading since it looks like DCN30 code depends on next version DCN301, which in fact is vice-versa. [How] Refactor the naming to ABM_MASK_SH_LIST_DCN30. v2: squash in build fixes (Alex) Signed-off-by: Roman Li <roman.li@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-16drm/amd/display: Fix DCN302 makefileBhawanpreet Lakha
Some setups will fail to build. So copy dcn301 makefile setup which is known to work Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-16drm/amd/display: Use amdgpu_socbb.h instead of redefining structsBhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-12drm/amd/display: Add support for DCN302 (v2)Bhawanpreet Lakha
- add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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