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path: root/drivers/gpu/drm/amd/display/dc/dcn21
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2020-02-25drm/amd/display: Temporarily disable stutter on MPO transitionGeorge Shen
[Why] Underflow sometimes occurs during transition into MPO with stutter enabled. [How] When transitioning into MPO, disable stutter. Re-enable stutter within one frame. Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: optimize prgoram wm and clksYongqiang Sun
[Why] In some display configuration like 1080P monitor playing a 1080P video, if user use ALT+F4 to exit Movie and TV, there is a chance clocks are same only water mark changed. Current clock optimization machanism will result in water mark keeps high after exit Movie and TV app. [How] Return if watermark need to be optimized when doing program watermark, perform the optimization after. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add driver support for enabling PSR on DMCUBWyatt Wood
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Add infrastructure to enable and disable PSR on DMCUB. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add function pointers for panel related hw functionsAnthony Koo
[Why] Make panel backlight and power on/off functions into hardware specific function pointers [How] Add function pointers for panel related hw functions - is_panel_powered_on - is_panel_backlight_on Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Add initialitions for PLL2 clock sourceIsabel Zhang
[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: fix workaround for incorrect double buffer register for DLG ↵Tony Cheng
ADL and TTU [Why] these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern. [How] there is a driver bug where we don't check for 0, which is uninitialzed HW default. since 0 is smaller than any value we need to program, driver end up with not programming these registers Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: fix inputting clk lvl into dml for RNEric Yang
[Why] Previous logic is only good for 15W parts. Other configuration need a smarter logic to match clk levels with pp table in the fuse. [How] Cache all 8 DPM level's clock data, find lvl that match each pstate in the pp table and build input into DML base on that Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Added locking for atomic update stream and update planesAnthony Koo
[Why] Screen flickering when HDR switches between FP16 and ARGB2101010 [How] Moved pipe_control_lock so stream update and plane update occur atomically Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Lucy Li <lucy.li@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Split program front end part that occur outside lockAnthony Koo
[Why] Eventually want to lock at a higher level in stack. To do this, we need to be able to isolate the parts that need to be done after pipe unlock. [How] Split out programming that is done post unlock. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-22drm/amd/display: changed max_downscale_src_width to 4096.Isabel Zhang
[Why] MPO isn't enabled on some 4k videos due to video source width is 4096 and the current limit is 3840. [How] Changed the limit to 4096. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-22drm/amd/display: fix rotation_angle to use enum valuesBrandon Syu
[Why] Hardcoded fixed values are not proper. [How] Use enum values instead of fixed numbers. Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Only program surface flip for video plane via dmcubYongqiang Sun
Only need to do surface flip for video plane via dmcub. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Use SMU ClockTable Values for DML CalculationsSung Lee
[Why] DML Initialization was previously done on dcn21_resource initialization. This meant that DML soc struct was populated with hardcoded values. [How] Move DML initialization to after updating bounding box, to use clock table values from SMU. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Add w/a to reset PHY before link training in verify_link_capGeorge Shen
[Why] PHY will sometimes be in bad state on hotplugging display from USB-C dongle. [How] Add additional calls to disable and then enable PHY before link training starts during verify_link_cap. Signed-off-by: George Shen <george.shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Refactor surface flip programmingYongqiang Sun
Rework surface programming for RN to separate preparing parameters and register programming. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Indirect reg read macro with shift and maskNoah Abradjian
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: programing surface flip by dmcub.Yongqiang Sun
Programming surface flip addresses via dmcub uC for optimizing the data flush. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Driverside changes to support PSR in DMCUBWyatt Wood
[Why] Moving PSR from DMCU to DMCUB. [How] Add driverside PSR changes required to send inbox messages to fw. These changes are non-functional until the psr structure allocation is uncommented. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Fix double buffering in dcn2 ICSCNoah Abradjian
[Why] When rapidly adjusting video brightness, screen tearing was observed. This was due to overwritten values in ICSC registers. In dcn10, this issue had been fixed by implementing double buffering via alternating ICSC modes. However, the second register set used in dcn1 doesn't exist in dcn2. [How] Create new program_input_csc for dcn20. Use ICSC_B registers instead of COMA registers as second set. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Add double buffering to dcn20 OCSCNoah Abradjian
[Why] When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed. This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by implementing double buffering by alternating OCSC modes. [How] Alternate which OCSC registers are used by switching modes each time. This double buffers the CSC writes. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: fix chroma vp wa corner caseEric Yang
[Why] Previous implementation we may have residual chroma address offset if transition from wa enable -> wa disable. [How] Clear address offset cache when viewport updates. Also update the vp size check condition to account for rotation angle Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/display: Update extended timeout support for DCN20 and DCN21abdoulaye berthe
[Why] DCN21 and DCN2 extended timeout support cap is not set correctly. [How] Set extended timeout support for ASIC families to their right values. Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/display: Fix update_bw_bounding_box CalcsSung Lee
[Why] Previously update_bw_bounding_box for RN was commented out due to incorrect values causing BSOD on Hybrid Graphics. However, commenting out this function also may cause issues such as underflow in certain cases such as 2x4K displays. [How] Fix dram_speed_mts calculations. Update from proper index of clock_limits[] Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/display: Collapse resource arrays when pipe is disabledNoah Abradjian
[Why] Currently, pipe resources are assigned to an index that matches the pipe position. However, if pipe 1 or 2 is disabled, there will be a gap in the arrays which causes a crash when iterating based on pipe_count. [How] Fix resource construct to assign resources to minimum available array index. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/display: update chroma viewport waEric Yang
[Why] Need previously implemented chroma vp wa to work for rotation cases. [How] Implement rotation specific wa. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/display: disable lttpr for RNabdoulaye berthe
Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/display: add missing dcn link encoder regsRoman Li
[Why] The earlier change: "check phy dpalt lane count config" uses link encoder registers not defined properly. That caused regression with mst-enabled display not lighting up. [How] Add missing reg definitions. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18amdgpu: Enable initial DCN support on POWERTimothy Pearson
DCN requires floating point support to operate. Add the appropriate x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN. Note that the current DC20 code doesn't contain all required FPU wrappers on x86 or POWER, so this patch is insufficient to fully enable DC20 on POWER. v2: s/X86_64/X86/g to retain previous behavior. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18amdgpu: Prepare DCN floating point macros for generic arch supportTimothy Pearson
Introduce DC_FP_START()/DC_FP_END() macros to help enable floating point kernel mode support across various architectures. v2: move copyright update to commit which adds the changes Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-17Merge tag 'drm-next-5.6-2019-12-11' of ↵Daniel Vetter
git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.6-2019-12-11: amdgpu: - Add MST atomic routines - Add support for DMCUB (new helper microengine for displays) - Add OEM i2c support in DC - Use vstartup for vblank events on DCN - Simplify Kconfig for DC - Renoir fixes for DC - Clean up function pointers in DC - Initial support for HDCP 2.x - Misc code cleanups - GFX10 fixes - Rework JPEG engine handling for VCN - Add clock and power gating support for JPEG - BACO support for Arcturus - Cleanup PSP ring handling - Add framework for using BACO with runtime pm to save power - Move core pci state handling out of the driver for pm ops - Allow guest power control in 1 VF case with SR-IOV - SR-IOV fixes - RAS fixes - Support for power metrics on renoir - Golden settings updates for gfx10 - Enable gfxoff on supported navi10 skus - Update MAINTAINERS amdkfd: - Clean up generational gfx code - Fixes for gfx10 - DIQ fixes - Share more code with amdgpu radeon: - PPC DMA fix - Register checker fixes for r1xx/r2xx - Misc cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191211223020.7510-1-alexander.deucher@amd.com
2019-12-11drm/amdgpu: fix license on Kconfig and MakefilesAlex Deucher
amdgpu is MIT licensed. Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier - Makefile/Kconfig") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-11drm/amd/display: include linux/slab.h where neededArnd Bergmann
Calling kzalloc() and related functions requires the linux/slab.h header to be included: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 'dcn21_ipp_create': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? [-Werror=implicit-function-declaration] kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); A lot of other headers also miss a direct include in this file, but this is the only one that causes a problem for now. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-11drm/amdgpu: fix license on Kconfig and MakefilesAlex Deucher
amdgpu is MIT licensed. Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier - Makefile/Kconfig") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-10drm/amd/display: include linux/slab.h where neededArnd Bergmann
Calling kzalloc() and related functions requires the linux/slab.h header to be included: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 'dcn21_ipp_create': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? [-Werror=implicit-function-declaration] kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); A lot of other headers also miss a direct include in this file, but this is the only one that causes a problem for now. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update dispclk and dppclk vco frequencyEric Yang
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fix DalDramClockChangeLatencyNs overrideJoseph Gravenor
[why] pstate_latency_us never gets updated from the hard coded value in rn_clk_mgr.c [how] update the wm table's values before we do calculations with them Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update sr and pstate latencies for RenoirEric Yang
[Why] DF team has produced more optimized latency numbers. [How] Add sr latencies to the wm table, use different latencies for different wm sets. Also fix bb override from registery key for these latencies. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update dispclk and dppclk vco frequencyEric Yang
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Limit NV12 chroma workaroundAnthony Koo
[Why] It is causing green Line at the bottom of SDR 480p MPO playback [How] Limit workaround to vertical > 512 Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Disable chroma viewport w/a when rotated 180 degreesMichael Strauss
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the MPO plane is rotated 180 degrees, the viewport is read in reverse. Since the workaround increases viewport size, when reading in reverse it causes a vertical chroma offset. [HOW] Pass rotation value to viewport set functions Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Wrong ifdef guards were used around DML validationJaehyun Chung
[Why] Wrong guards were causing the debug option not to run. [How] Changed the guard to the correct one, matching the rq, ttu, dlg regs struct members that need to be guarded. Also log a message when validation starts. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fix DalDramClockChangeLatencyNs overrideJoseph Gravenor
[why] pstate_latency_us never gets updated from the hard coded value in rn_clk_mgr.c [how] update the wm table's values before we do calculations with them Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: add separate of private hwss functionsAnthony Koo
[Why] Some function pointers in the hwss function pointer table are meant to be hw sequencer entry points to be called from dc. However some of those function pointers are not meant to be entry points, but instead used as a code reuse/inheritance tool called directly by other hwss functions, not by dc. Therefore, we want a more clear separation of which functions we determine to be interface functions vs the functions we use within hwss. [How] DC interface functions will be stored in: struct hw_sequencer_funcs Functions used within HWSS will be stored in: struct hwseq_private_funcs Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update sr and pstate latencies for RenoirEric Yang
[Why] DF team has produced more optimized latency numbers. [How] Add sr latencies to the wm table, use different latencies for different wm sets. Also fix bb override from registery key for these latencies. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/display: DML Validation Dump/Check with LoggingJaehyun Chung
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are programming incorrect values and may help differentiate DAL issues from HW issues. [How] Dump relevant registers for each pipe with active stream. Compare current reg values with the converted DML output. Log mismatches when found. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/display: cleanup of function pointer tablesAnthony Koo
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions [How] 1. Make function pointer table init in its own init.c file 2. Remove other scenarios in hwseq.c file that need to include headers of other DCN versions. (If needed, it should have been done via the function pointers) Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/display: cleanup of construct and destruct funcsAnthony Koo
[Why] Too many construct functions which makes searching difficult, especially on some debuggers. [How] Append all construct and destruct functions with dcn number and object type to make each construct function name unique Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/display: Changes in dc to allow full update in some casesAlvin Lee
Changes in dc to allow for different cases where full update is required. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/display: Renoir chroma viewport WA Read the correct registerJoseph Gravenor
[why] Before we were reading registers specific to luma size, which caused a black line to appear on the screen from time to time, as although the luma row height is generally the same as the chroma row height for the video case, it will sometimes be one more [how] Read the register specific for the chroma size Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/display: Renoir chroma viewport WA change formulaJoseph Gravenor
[why] we want to increase the pte row plus 1 line if chroma viewport height is integer multiple of the pte row height [how] instead of ceiling viewport height, we floor it. this allows us to accommodate both cases: those where the chroma viewport height is integer multiple of the pte row height and those where it is not Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 05:20:15 +0000