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2022-05-16dmaengine: idxd: Separate user and kernel pasid enablingDave Jiang
The idxd driver always gated the pasid enabling under a single knob and this assumption is incorrect. The pasid used for kernel operation can be independently toggled and has no dependency on the user pasid (and vice versa). Split the two so they are independent "enabled" flags. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/165231431746.986466.5666862038354800551.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-16dmaengine: idxd: Fix the error handling path in idxd_cdev_register()Christophe JAILLET
If a call to alloc_chrdev_region() fails, the already allocated resources are leaking. Add the needed error handling path to fix the leak. Fixes: 42d279f9137a ("dmaengine: idxd: add char driver to expose submission portal to userland") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/1b5033dcc87b5f2a953c413f0306e883e6114542.1650521591.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-16dmaengine: tegra: Use platform_get_irq() to get IRQ resourceAkhil R
Use platform_irq_get() instead platform_get_resource() for IRQ resource to fix the probe failure. platform_get_resource() fails to fetch the IRQ resource as it might not be ready at that time. platform_irq_get() is also the recommended way to get interrupt as it directly gives the IRQ number and no conversion from resource is required. Fixes: ee17028009d4 ("dmaengine: tegra: Add tegra gpcdma driver") Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20220505091440.12981-1-akhilrajeev@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-22dma: omap: hide legacy interfaceArnd Bergmann
The legacy interface for omap-dma is only used on OMAP1, and the same is true for the non-DT case. Make both of these conditional on CONFIG_ARCH_OMAP1 being set to simplify the dependency. The non-OMAP stub functions in include/linux/omap-dma.h are note needed any more either now, because they are only called on OMAP1. Acked-by: Tony Lindgren <tony@atomide.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-22dmaengine: mv_xor_v2 : Move spin_lock_bh() to spin_lock()Yunbo Yu
It is unnecessary to call spin_lock_bh() for that you are already in a tasklet. Signed-off-by: Yunbo Yu <yuyunbo519@gmail.com> Link: https://lore.kernel.org/r/20220420122754.148359-1-yuyunbo519@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-22dmaengine: idxd: refactor wq driver enable/disable operationsDave Jiang
Move the core driver operations from wq driver to the drv_enable_wq() and drv_disable_wq() functions. The move should reduce the wq driver's knowledge of the core driver operations and prevent code confusion for future wq drivers. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/165047301643.3841827.11222723219862233060.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-22dmaengine: ti: k3-psil-am62: Update PSIL thread for saul.Jayesh Choudhary
Correct the RX PSIL thread for sa3ul. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Fixes: 5ac6bfb587772 ("dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data") Link: https://lore.kernel.org/r/20220421065323.16378-1-j-choudhary@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-22dmaengine: ptdma: statify pt_tx_statusVinod Koul
LKP bot reports a new warning: Warning: drivers/dma/ptdma/ptdma-dmaengine.c:262:1: warning: no previous prototype for 'pt_tx_status' [-Wmissing-prototypes] pt_tx_status() should be static, so declare as such. Reported-by: kernel test robot <lkp@intel.com> Fixes: d965068259d1 ("dmaengine: PTDMA: support polled mode") Link: https://lore.kernel.org/r/20220421052407.745637-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: hidma: In hidma_prep_dma_memset treat value as a single byteBen Walker
The value parameter is a single byte, so duplicate it to the 8 byte range that is used as the pattern. Signed-off-by: Ben Walker <benjamin.walker@intel.com> Cc: Sinan Kaya <okaya@kernel.org> Link: https://lore.kernel.org/r/20220301182551.883474-5-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: at_xdmac: In at_xdmac_prep_dma_memset, treat value as a single byteBen Walker
The value passed in to .prep_dma_memset is to be treated as a single byte repeating pattern. Signed-off-by: Ben Walker <benjamin.walker@intel.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220301182551.883474-4-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: at_hdmac: In atc_prep_dma_memset, treat value as a single byteBen Walker
The value passed in to .prep_dma_memset is to be treated as a single byte repeating pattern. Signed-off-by: Ben Walker <benjamin.walker@intel.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220301182551.883474-3-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: move wq irq enabling to after device enableDave Jiang
Move the calling of request_irq() and other related irq setup code until after the WQ is successfully enabled. This reduces the amount of setup/teardown if the wq is not configured correctly and cannot be enabled. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164642777730.179702.1880317757087484299.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: skip clearing device context when device is read-onlyDave Jiang
If the device shows up as read-only configuration, skip the clearing of the state as the context must be preserved for device re-enable after being disabled. Fixes: 0dcfe41e9a4c ("dmanegine: idxd: cleanup all device related bits after disabling device") Reported-by: Tony Zhu <tony.zhu@intel.com> Tested-by: Tony Zhu <tony.zhu@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971479479.2200566.13980022473526292759.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: add RO check for wq max_transfer_size writeDave Jiang
Block wq_max_transfer_size_store() when the device is configured as read-only and not configurable. Fixes: d7aad5550eca ("dmaengine: idxd: add support for configurable max wq xfer size") Reported-by: Bernice Zhang <bernice.zhang@intel.com> Tested-by: Bernice Zhang <bernice.zhang@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971488154.2200913.10706665404118545941.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: add RO check for wq max_batch_size writeDave Jiang
Block wq_max_batch_size_store() when the device is configured as read-only and not configurable. Fixes: e7184b159dd3 ("dmaengine: idxd: add support for configurable max wq batch size") Reported-by: Bernice Zhang <bernice.zhang@intel.com> Tested-by: Bernice Zhang <bernice.zhang@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971493551.2201159.1942042593642155209.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: fix retry value to be constant for duration of function callDave Jiang
When retries is compared to wq->enqcmds_retries each loop of idxd_enqcmds(), wq->enqcmds_retries can potentially changed by user. Assign the value of retries to wq->enqcmds_retries during initialization so it is the original value set when entering the function. Fixes: 7930d8553575 ("dmaengine: idxd: add knob for enqcmds retries") Suggested-by: Dave Hansen <dave.hansen@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/165031760154.3658664.1983547716619266558.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: match type for retries var in idxd_enqcmds()Dave Jiang
wq->enqcmds_retries is defined as unsigned int. However, retries on the stack is defined as int. Change retries to unsigned int to compare the same type. Fixes: 7930d8553575 ("dmaengine: idxd: add knob for enqcmds retries") Suggested-by: Thiago Macieira <thiago.macieira@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/165031747059.3658198.6035308204505664375.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: dw-edma: Fix inconsistent indentingJiapeng Chong
Eliminate the follow smatch warning: drivers/dma/dw-edma/dw-edma-v0-core.c:419 dw_edma_v0_core_start() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20220413023442.18856-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: tegra: Remove unused including <linux/version.h>Jiapeng Chong
Eliminate the follow versioncheck warning: ./drivers/dma/tegra186-gpc-dma.c: 21 linux/version.h not needed. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20220413083842.69845-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: add verification of DMA_INTERRUPT capability for dmatestDave Jiang
Looks like I forgot to add DMA_INTERRUPT cap setting to the idxd driver and dmatest is still working regardless of this mistake. Add an explicit check of DMA_INTERRUPT capability for dmatest to make sure the DMA device being used actually supports interrupt before the test is launched and also that the driver is programmed correctly. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164978679251.2361020.5856734256126725993.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: mediatek: mtk-hsdma: use NULL instead of using plain integer as ↵Haowen Bai
pointer This fixes the following sparse warnings: drivers/dma/mediatek/mtk-hsdma.c:604:26: warning: Using plain integer as NULL pointer Signed-off-by: Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1649750340-30777-1-git-send-email-baihaowen@meizu.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: pl08x: drop the useless functionHaowen Bai
Unneeded variable: "retval". Return "NULL" , so we have to make code clear. better way, drop the function. Signed-off-by: Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1649726180-13133-1-git-send-email-baihaowen@meizu.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: set max_xfer and max_batch for RO deviceDave Jiang
Load the max_xfer_size and max_batch_size values from the values read from registers to the shadow variables. This will allow the read-only device to display the correct values for the sysfs attributes. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971507673.2201761.11244446608988838897.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: set DMA_INTERRUPT cap bitDave Jiang
Even though idxd driver has always supported interrupt, it never actually set the DMA_INTERRUPT cap bit. Rectify this mistake so the interrupt capability is advertised. Reported-by: Ben Walker <benjamin.walker@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971497859.2201379.17925303210723708961.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: jz4780: set DMA maximum segment sizeAidan MacDonald
Set the maximum segment size, since the hardware can do transfers larger than the default 64 KiB returned by dma_get_max_seg_size(). The maximum segment size is limited by the 24-bit transfer count field in DMA descriptors. The number of bytes is equal to the transfer count times the transfer size unit, which is selected by the driver based on the DMA buffer address and length of the transfer. The size unit can be as small as 1 byte, so set the maximum segment size to 2^24-1 bytes to ensure the transfer count will not overflow regardless of the size unit selected by the driver. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220411153618.49876-1-aidanmacdonald.0x0@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: PTDMA: support polled modeIlya Novikov
If the DMA_PREP_INTERRUPT flag is not provided, run in polled mode, which significantly improves IOPS: more than twice on chunks < 4K. Signed-off-by: Ilya Novikov <i.m.novikov@yadro.com> Link: https://lore.kernel.org/r/20220413113733.59041-1-i.m.novikov@yadro.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: plx_dma: Move spin_lock_bh() to spin_lock()Yunbo Yu
It is unnecessary to call spin_lock_bh() if you are already in a tasklet. Signed-off-by: Yunbo Yu <yuyunbo519@gmail.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Link: https://lore.kernel.org/r/20220418142021.1241558-1-yuyunbo519@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-19dmaengine: imx-sdma: Add multi fifo supportSascha Hauer
The i.MX SDMA engine can read from / write to multiple successive hardware FIFO registers, referred to as "Multi FIFO support". This is needed for the micfil driver and certain configurations of the SAI driver. This patch adds support for this feature. The number of FIFOs to read from / write to must be communicated from the client driver to the SDMA engine. For this the struct dma_slave_config::peripheral_config field is used. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220414162249.3934543-12-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-19dmaengine: imx-sdma: error out on unsupported transfer typesSascha Hauer
The i.MX SDMA driver currently silently ignores unsupported transfer types. These transfer types are specified in the dma channel description in the device tree, so they should really be checked. Issue a message and error out when we hit unsupported transfer types. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220414162249.3934543-11-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-19dmaengine: imx: Move header to include/dma/Sascha Hauer
The i.MX DMA drivers are device tree only, nothing in include/linux/platform_data/dma-imx.h has platform_data in it, so move the file to include/linux/dma/imx-dma.h. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220414162249.3934543-10-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-13dmaengine: qcom: gpi: Add SM8350 supportBjorn Andersson
The Qualcomm SM8350 platform does, like the SM8450, provide a set of GPI controllers with an ee-offset of 0x10000. Add this to the driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220412212959.2385085-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-13dmaengine: qcom: gpi: Add support for ee_offsetVinod Koul
Controller on newer SoCs like SM8450 have registers at at offset. Add ee_offset to driver_data and add this compatible for the driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220406132508.1029348-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-13dmaengine: qcom: gpi: set chain and link flag for duplexVinod Koul
Newer platforms seem to have strict requirement for TRE flags which causes transaction to timeout. This was resolved to missing chain and link flag for duplex spi transaction. So add these two flags. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220406132508.1029348-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-12dmaengine: dw-edma: Fix unaligned 64bit accessHerve Codina
On some arch (ie aarch64 iMX8MM) unaligned PCIe accesses are not allowed and lead to a kernel Oops. [ 1911.668835] Unable to handle kernel paging request at virtual address ffff80001bc00a8c [ 1911.668841] Mem abort info: [ 1911.668844] ESR = 0x96000061 [ 1911.668847] EC = 0x25: DABT (current EL), IL = 32 bits [ 1911.668850] SET = 0, FnV = 0 [ 1911.668852] EA = 0, S1PTW = 0 [ 1911.668853] Data abort info: [ 1911.668855] ISV = 0, ISS = 0x00000061 [ 1911.668857] CM = 0, WnR = 1 [ 1911.668861] swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000040ff4000 [ 1911.668864] [ffff80001bc00a8c] pgd=00000000bffff003, pud=00000000bfffe003, pmd=0068000018400705 [ 1911.668872] Internal error: Oops: 96000061 [#1] PREEMPT SMP ... The llp register present in the channel group registers is not aligned on 64bit. Fix unaligned 64bit access using two 32bit accesses Fixes: 04e0a39fc10f ("dmaengine: dw-edma: Add writeq() and readq() for 64 bits architectures") Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220225120252.309404-1-herve.codina@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-12dmaengine: mediatek:Fix PM usage reference leak of ↵zhangqilong
mtk_uart_apdma_alloc_chan_resources pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to putting operation will result in reference leak here. We fix it: 1) Replacing it with pm_runtime_resume_and_get to keep usage counter balanced. 2) Add putting operation before returning error. Fixes:9135408c3ace4 ("dmaengine: mediatek: Add MediaTek UART APDMA support") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20220319022142.142709-1-zhangqilong3@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: Remove a useless mutexChristophe JAILLET
According to lib/idr.c, The IDA handles its own locking. It is safe to call any of the IDA functions without synchronisation in your code. so the 'chan_mutex' mutex can just be removed. It is here only to protect some ida_alloc()/ida_free() calls. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/7180452c1d77b039e27b6f9418e0e7d9dd33c431.1644140845.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: imx-sdma: Fix error checking in sdma_event_remapMiaoqian Lin
of_parse_phandle() returns NULL on errors, rather than error pointers. Using NULL check on grp_np to fix this. Fixes: d078cd1b4185 ("dmaengine: imx-sdma: Add imx6sx platform support") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220308064952.15743-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: tegra: Add tegra gpcdma driverAkhil R
Adding GPC DMA controller driver for Tegra. The driver supports dma transfers between memory to memory, IO peripheral to memory and memory to IO peripheral. Co-developed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Co-developed-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220225132044.14478-3-akhilrajeev@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: idxd: remove trailing white space on input str for wq nameDave Jiang
Add string processing with strim() in order to remove trailing white spaces that may be input by user for the wq->name. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164789525123.2799661.13795829125221129132.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dma: at_xdmac: fix a missing check on list iteratorXiaomeng Tong
The bug is here: __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); The list iterator 'desc' will point to a bogus position containing HEAD if the list is empty or no element is found. To avoid dev_dbg() prints a invalid address, use a new variable 'iter' as the list iterator, while use the origin variable 'desc' as a dedicated pointer to point to the found element. Cc: stable@vger.kernel.org Fixes: 82e2424635f4c ("dmaengine: xdmac: fix print warning on dma_addr_t variable") Signed-off-by: Xiaomeng Tong <xiam0nd.tong@gmail.com> Link: https://lore.kernel.org/r/20220327061154.4867-1-xiam0nd.tong@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: stm32-mdma: check the channel availability (secure or not)Amelie Delaunay
STM32_MDMA_CCR bit[8] is used to enable Secure Mode (SM). If this bit is set, it means that all the channel registers are write-protected. So the channel is not available for Linux use. Add stm32_mdma_filter_fn() callback filter and give it to __dma_request_chan (instead of dma_get_any_slave_channel()), to exclude the channel if it is marked Secure. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220330103645.99969-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: bestcomm: Prepare cleanup of powerpc's asm/prom.hChristophe Leroy
powerpc's asm/prom.h brings some headers that it doesn't need itself. In order to clean it up, first add missing headers in users of asm/prom.h Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/f98acba303489bdf003e7256460696225b00702e.1648833428.git.christophe.leroy@csgroup.eu Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: ep93xx: Remove redundant word in commentjianchunfu
Remove the second 'to' which is repeated. Signed-off-by: jianchunfu <jianchunfu@cmss.chinamobile.com> Link: https://lore.kernel.org/r/20220403123120.7794-1-jianchunfu@cmss.chinamobile.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: idxd: don't load pasid config until neededDave Jiang
The driver currently programs the system pasid to the WQ preemptively when system pasid is enabled. Given that a dwq will reprogram the pasid and possibly a different pasid, the programming is not necessary. The pasid_en bit can be set for swq as it does not need pasid programming but needs the pasid_en bit. Remove system pasid programming on device config write. Add pasid programming for kernel wq type on wq driver enable. The char dev driver already reprograms the dwq on ->open() call so there's no change. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164935607115.1660372.6734518676950372366.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: mediatek-cqdma: Use platform_get_irq() to get the interruptLad Prabhakar
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220404155557.27316-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: mediatek: mtk-hsdma: Use platform_get_irq() to get the interruptLad Prabhakar
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220404155557.27316-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: nbpfaxi: Use platform_get_irq_optional() to get the interruptLad Prabhakar
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_optional(). There are no non-DT users for this driver so interrupt range (irq_res->start-irq_res->end) is no longer required and with DT we will be sure it will be a single IRQ resource for each index. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220404155557.27316-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11dmaengine: imx-sdma: fix init of uart scriptsKevin Groeneveld
Commit b98ce2f4e32b ("dmaengine: imx-sdma: add uart rom script") broke uart rx on imx5 when using sdma firmware from older Freescale 2.6.35 kernel. In this case reading addr->uartXX_2_mcu_addr was going out of bounds of the firmware memory and corrupting the uart script addresses. Simply adding a bounds check before accessing addr->uartXX_2_mcu_addr does not work as the uartXX_2_mcu_addr members are now beyond the size of the older firmware and the uart addresses would never be populated in that case. There are other ways to fix this but overall the logic seems clearer to me to revert the uartXX_2_mcu_ram_addr structure entries back to uartXX_2_mcu_addr, change the newer entries to uartXX_2_mcu_rom_addr and update the logic accordingly. I have tested this patch on: 1. An i.MX53 system with sdma firmware from Freescale 2.6.35 kernel. Without this patch uart rx is broken in this scenario, with the patch uart rx is restored. 2. An i.MX6D system with no external sdma firmware. uart is okay with or without this patch. 3. An i.MX8MM system using current sdma-imx7d.bin firmware from linux-firmware. uart is okay with or without this patch and I confirmed the rom version of the uart script is being used which was the intention and reason for commit b98ce2f4e32b ("dmaengine: imx-sdma: add uart rom script") in the first place. Fixes: b98ce2f4e32b ("dmaengine: imx-sdma: add uart rom script") Cc: stable@vger.kernel.org Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20220410223118.15086-1-kgroeneveld@lenbrook.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-08dmaengine: idxd: fix device cleanup on disableDave Jiang
There are certain parts of WQ that needs to be cleaned up even after WQ is disabled during the device disable. Those are the unchangeable parts for a WQ when the device is still enabled. Move the cleanup outside of WQ state check. Remove idxd_wq_disable_cleanup() inside idxd_wq_device_reset_cleanup() since only the unchangeable parts need to be cleared. Fixes: 0f225705cf65 ("dmaengine: idxd: fix wq settings post wq disable") Reported-by: Tony Zhu <tony.zhu@intel.com> Tested-by: Tony Zhu <tony.zhu@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164919561905.1455025.13542366389944678346.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-08dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2LLad Prabhakar
The DMAC block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220406080417.14593-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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