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2016-10-27Merge branch 'clk-fixes' into clk-nextStephen Boyd
* clk-fixes: clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUT
2016-10-27clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUTMarek Szyprowski
The Exynos PMU node is an interrupt, clock and PMU (Power Management Unit) controller, and these functionalities are supported by different drivers that matches the same compatible strings. Since commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks") the OF core flags clock controllers registered with the CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same compatible string will not be registered. This prevents the PMU platform device to be created, so the Exynos PMU driver is never probed. This breaks (among other things) Suspend-to-RAM. Fix this by changing CLKOUT driver initialization method to CLK_OF_DECLARE_DRIVER(), which doesn't clear the OF_POPULATED flag, so later a platform device is created and the Exynos PMU platform driver can be be probed properly. Fixes: 989eafd0b609 ("clk: core: Avoid double initialization of clocks") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-25clk: sunxi-ng: Implement minimum for multipliersMaxime Ripard
Allow the CCU drivers to specify a multiplier for their clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-25clk: sunxi-ng: Add minimums for all the relevant structures and clocksMaxime Ripard
Modify the current clocks we have to be able to specify the minimum for each clocks we support, just like we support the max. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-25clk: sunxi-ng: Finish to convert to structures for argumentsMaxime Ripard
Some clocks still use an explicit list of arguments, which make it a bit more tedious to add new parameters. Convert those over to a structure pointer argument to add as many arguments as possible without having to many noise in our patches, or a very long list of arguments. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-25clk: sunxi-ng: Remove the use of rational computationsMaxime Ripard
While the rational library works great, it doesn't really allow us to add more constraints, like the minimum. Remove that in order to be able to deal with the constraints we'll need. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-23Merge branch 'clk-next-oxnas' into clk-nextMichael Turquette
2016-10-23clk: oxnas: Add OX820 Gate clocksNeil Armstrong
Add support for the Oxford Semiconductor OX820 SoC gate clocks along the OX810SE SoC support. This rework on concerns the gate clocks since they are different. Future PLL handling code will be added for OX820. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-6-narmstrong@baylibre.com
2016-10-23clk: oxnas: Refactor to make use of devm_clk_hw_register()Neil Armstrong
Make usage of static tables identified by the OF match table to feed devm_clk_hw_register() and use of_clk_add_hw_provider(). This structure is cleaner and simplifies adding new SoC support while having common probe and gate ops code. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-5-narmstrong@baylibre.com
2016-10-23clk: oxnas: Rename to clk_oxnas_gateNeil Armstrong
Rename clock ops to clk_oxnas_gate in ops and structures. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-4-narmstrong@baylibre.com
2016-10-21clk: rockchip: Use clock ids for cpu and peri clocks on rk3066Paweł Jarosz
Add bindings for ACLK_CPU, HCLK_CPU, PCLK_CPU, ACLK_PERI, HCLK_PERI, PCLK_PERI. We need this to init it's rate at boot time. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-21clk: rockchip: add 533.25MHz to rk3399 clock rates tableXing Zheng
We need to get the accurate 533.25MHz for the DP display. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-20clk: at91: Fix a return value in case of errorChristophe JAILLET
If 'clk_hw_register()' fails, it is likely that we expect to return an error instead of a valid pointer (which would mean success). Fix commit f5644f10dcfb ("clk: at91: Migrate to clk_hw based registration and OF APIs") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-20clk: sunxi-ng: Rename the internal structuresMaxime Ripard
Rename the structures meant to be embedded in other structures to make it consistent with the mux structure name Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-19clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCsMasahiro Yamada
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-19clk: uniphier: fix memory overrun bugMasahiro Yamada
The first loop of this "for" statement writes memory beyond the allocated clk_hw_onecell_data. It should be: for (clk_num--; clk_num >= 0; clk_num--) ... Or more simply: while (--clk_num >= 0) ... Fixes: 734d82f4a678 ("clk: uniphier: add core support code for UniPhier clock driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-19clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parentChen-Yu Tsai
On the A31, the DMA engine only works if AHB1 is clocked from PLL6. In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked from the CPU clock, and cpufreq is working, we get an unstable timer. Force the AHB1 clock to use PLL6 as its parent. Previously this was done in the device tree with the assigned-clocks and assigned-clocks-parent bindings. However with this new monolithic driver, the system critical clocks aren't exported through the device tree. The alternative is to force this setting in the driver before the clocks are registered. This is also done in newer versions of mainline U-boot. But people still using an older version, or even the vendor version, can still hit this issue. Hence the need to do it in the kernel as well. Reported-by: Hans de Goede <hdegoede@redhat.com> Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-18clk: pxa25x: OSTIMER0 clocks from the main oscillatorRussell King - ARM Linux
The OSTIMER0 clock ticks at the main oscillator rate, not the 32kHz oscillator rate. Ensure that it is parented to the main oscillator. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-10-17clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock initShawn Guo
The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but also reset controller. It worked fine that single sysctrl/mediactrl device node in DT can be used to initialize clock driver and populate platform device for reset controller. But it stops working after commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks") gets merged. The commit sets flag OF_POPULATED during clock initialization to skip the platform device populating for the same device node. On hi6220, it effectively makes hi6220-sysctrl reset driver not probe any more. The patch changes hi6220 sysctrl and mediactrl clock init macro from CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using the same hardware block can continue working. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: mvebu: armada-37xx-periph: Fix the clock gate flagGregory CLEMENT
For the gate part of the peripheral clock setting the bit disables the clock and clearing it enables the clock. This is not the default behavior of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.Eric Anholt
Fixes setting low-resolution video modes on HDMI. Now the PLLH_PIX divider adjusts itself until the PLLH is within bounds. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: max77686: fix number of clocks setup for clk_hw based registrationJavier Martinez Canillas
The commit 9b4cac33adc7 ("clk: max77686: Migrate to clk_hw based OF and registration APIs") converted the driver to use the new provider API to register clocks using clk_hw. But unfortunately, in the conversion it missed to set the num_clks value which lead to the following error when trying to register a clk provider: [ 1.963782] of_clk_max77686_get: invalid index 0 [ 1.967460] ERROR: could not get clock /rtc@10070000:rtc_src(1) [ 1.973638] s3c-rtc 10070000.rtc: failed to find rtc source clock Fix it by correctly set the max77686_clk_driver_data num_clks member. Fixes: 9b4cac33adc7 ("clk: max77686: Migrate to clk_hw based OF and registration APIs") Reported-by: Markus Reichl <m.reichl@fivetechno.de> Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: mvebu: armada-37xx-periph: Fix the clock provider registrationGregory CLEMENT
While trying using a peripheral clock on a driver, I saw that the clock pointer returned by the provider was NULL. The problem was a missing indirection. It was the pointer stored in the hws array which needed to be updated not the value it contains. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: mediatek: Add hardware dependencyJean Delvare
Only propose the mediatek clock drivers on this platform, unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Shunli Wang <shunli.wang@mediatek.com> Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: samsung: clk-exynos-audss: Fix module autoloadJavier Martinez Canillas
If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias alias: platform:exynos-audss-clk After this patch: $ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias alias: platform:exynos-audss-clk alias: of:N*T*Csamsung,exynos5420-audss-clockC* alias: of:N*T*Csamsung,exynos5420-audss-clock alias: of:N*T*Csamsung,exynos5410-audss-clockC* alias: of:N*T*Csamsung,exynos5410-audss-clock alias: of:N*T*Csamsung,exynos5250-audss-clockC* alias: of:N*T*Csamsung,exynos5250-audss-clock alias: of:N*T*Csamsung,exynos4210-audss-clockC* alias: of:N*T*Csamsung,exynos4210-audss-clock Fixes: 4d252fd5719b ("clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver") Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: uniphier: fix type of variable passed to regmap_read()Masahiro Yamada
The 3rd argument of regmap_read() takes a pointer to unsigned int. This driver is saved just because u32 happens to be typedef'ed as unsigned int, but we should not rely on that fact. Change the variable type just in case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: uniphier: add system clock support for sLD3 SoCMasahiro Yamada
I do not know why, but I missed to add this compatible string in the initial commit of this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: renesas: cpg-mssr: Fix inverted debug checkGeert Uytterhoeven
The intention was to enable the checks if debugging is enabled, not disabled. Fixes: f793d1e51705b276 ("clk: shmobile: Add new CPG/MSSR driver core") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17clk: renesas: rcar-gen3-cpg: Always use readl()/writel()Geert Uytterhoeven
The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: renesas: cpg-mssr: Always use readl()/writel()Geert Uytterhoeven
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: renesas: r8a7796: Add I2C clocksUlrich Hecht
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17clk: renesas: r8a7796: Add HSCIF clocksUlrich Hecht
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17clk: renesas: r8a7796: Add SCIF clocksUlrich Hecht
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17clk: renesas: r8a7796: Add SYS-DMAC clocksUlrich Hecht
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-16clk: sunxi: mod0: improve function-level documentationJulia Lawall
Use the actual function name in the function documentation. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16clk: rockchip: don't return NULL when failing to register ddrclk branchShawn Lin
rockchip_clk_register_ddrclk should not return NULL when failing to call clk_register, otherwise rockchip_clk_register_branches prints "unknown clock type". The actual case is that it's a known clock type but we fail to register it, which may makes user confuse the reason of failure. And the pr_err here is pointless as rockchip_clk_register_branches will also print the similar message. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-07Merge tag 'armsoc-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an automotive SoC similar to the ⅹ8a7795 chip we already support, but the dts changes rely on a clock driver change that has been merged for v4.9 through the clk tree. - The Amlogic meson-gxbb (S905) platform gains support for a few drivers merged through our tree, in particular the network and usb driver changes are required and included here, and also the clk tree changes. - The Allwinner platforms have seen a large-scale change to their clk drivers and the dts file updates must come after that. This includes the newly added Nextthing GR8 platform, which is derived from sun5i/A13. - Some integrator (arm32) changes rely on clk driver changes. - A single patch for lpc32xx has no such dependency but wasn't added until just before the merge window" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) ARM: dts: lpc32xx: add device node for IRAM on-chip memory ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03 ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board ARM: dts: sun8i: add pinmux for UART1 at PG dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC dts: sun8i-h3: add pinmux definitions for I2C0-2 dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux dts: sun8i-h3: add pinmux definitions for UART2-3 ARM: dts: sun9i: a80-optimus: Disable EHCI1 ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ...
2016-10-07Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers: - The Qualcomm external bus interface 2 (EBI2), used in some of their mobile phone chips for connecting flash memory, LCD displays or other peripherals - Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the EFUSE based on that firmware interface. - Perf support for the AppliedMicro X-Gene performance monitor unit - Reset driver for STMicroelectronics STM32 - Reset driver for SocioNext UniPhier SoCs Aside from these, there are minor updates to SoC-specific bus, clocksource, firmware, pinctrl, reset, rtc and pmic drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) bus: qcom-ebi2: depend on HAS_IOMEM pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181 dt-bindings: EXYNOS: Add Exynos5433 PMU compatible clocksource: exynos_mct: Add the support for ARM64 perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver Documentation: Add documentation for APM X-Gene SoC PMU DTS binding MAINTAINERS: Add entry for APM X-Gene SoC PMU driver bus: qcom: add EBI2 driver bus: qcom: add EBI2 device tree bindings rtc: rtc-pm8xxx: Add support for pm8018 rtc nvmem: amlogic: Add Amlogic Meson EFUSE driver firmware: Amlogic: Add secure monitor driver soc: qcom: smd: Reset rx tail rather than tx memory: atmel-sdramc: fix a possible NULL dereference reset: hi6220: allow to compile test driver on other architectures reset: zynq: add driver Kconfig option reset: sunxi: add driver Kconfig option reset: stm32: add driver Kconfig option reset: socfpga: add driver Kconfig option ...
2016-10-07Merge tag 'armsoc-cleanup' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Arnd Bergmann: "The cleanups for v4.9 are a little larger that usual, but thankfully that is almost exclusively due to removing a significant number of files that have become obsolete after the still ongoing conversion of old board files to devicetree. - for mach-omap2, which is still the largest platform in arch/arm/, the conversion to DT is finally complete after the Nokia N900 is now fully supported there, along with the omap3 LDP, and we can remove those two board files. If no regressions are found, another large cleanup for the platform will happen as a follow-up, removing dead code and restructuring the platform based on being DT-only. - In mach-imx, similar work is ongoing, but has not come that far. This time, we remove the obsolete board file for the i.MX1 generation, which like i.MX25, i.MX5, i.MX6, and i.MX7 is now DT-only. The remaining board files are for i.MX2 and i.MX3 machines based on old ARM926 or ARM1136 cores that should work with DT in principle. - realview has just been converted from board files to DT, and a lot of code gets removed in the process. This is the last ARM/Keil/Versatile derived platform that was still using board files, the other ones being integrator, versatile and vexpress. We can probably merge the remaining code into a single directory in the near future. - clps711x had completed the conversion in v4.8, but we accidentally left the files in place that should have been deleted then" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits) ARM: select PCI_DOMAINS config from ARCH_MULTIPLATFORM ARM: stop *MIGHT_HAVE_PCI* config from being selected redundantly ARM: imx: (trivial) fix typo and grammar ARM: clps711x: remove extraneous files ARM: imx: use IS_ENABLED() instead of checking for built-in or module ARM: OMAP2+: use IS_ENABLED() instead of checking for built-in or module ARM: OMAP1: use IS_ENABLED() instead of checking for built-in or module ARM: imx: remove platform-mxc_rnga ARM: realview: imply device tree boot ARM: realview: no need to select SMP_ON_UP explicitly ARM: realview: delete the RealView board files ARM: imx: no need to select SMP_ON_UP explicitly ARM: i.MX: Move SOC_IMX1 into 'Device tree only' ARM: i.MX: Remove i.MX1 non-DT support ARM: i.MX: Remove i.MX1 Synertronixx SCB9328 board support ARM: i.MX: Remove i.MX1 Armadeus APF9328 board support ARM: mxs: remove obsolete startup code for TX28 ARM: i.MX31 iomux: remove duplicates with alternate name ARM: i.MX31 iomux: remove plain duplicates ARM: OMAP2+: Drop legacy board file for LDP ...
2016-09-23CLK: Add Loongson1C clock supportYang Ling
This patch adds clock support to Loongson1C SoC. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Acked-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-23clk: Loongson1: Make use of GENMASKKelvin Cheung
Make use of GENMASK instead of open coding the equivalent operation, and update the PLL formula. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-23clk: Loongson1: Update clocks of Loongson1BKelvin Cheung
This patch updates some clock names of Loongson1B, and adds AC97, DMA and NAND clock. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-23clk: Loongson1: Refactor Loongson1 clockKelvin Cheung
Factor out the common functions into loongson1/clk.c to support both Loongson1B and Loongson1C. And, put the rest into loongson1/clk-loongson1b.c. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-23clk: zx296718: register driver earlier with core_initcallShawn Guo
Clock driver should be registered with an earlier initcall than module_init which is used by most of client device drivers. Otherwise, probing of these client drivers will likely be deferred due to that calls into clk API will return -EPROBE_DEFER. Deferred probing is not a problem for most subsystems, but could bring some side effect for particular subsystem, like display. On ZX296718 platform, we get Linux logo and boot log lost from display device, just because the DRM/KMS driver gets -EPROBE_DEFER from devm_clk_get() call. Let's use core_initcall (qcom and a few other clk drivers use that) for driver registration to avoid those unnecessary -EPROBE_DEFER and get rid of the side effect with ZX296718 display system. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-22clk: mvebu: dynamically allocate resources in Armada CP110 system controllerMarcin Wojtas
Original commit, which added support for Armada CP110 system controller used global variables for storing all clock information. It worked fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k was introduced, the data got overwritten and corrupted. This patch fixes the issue by allocating resources dynamically in the driver probe and storing it as platform drvdata. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-22clk: mvebu: fix setting unwanted flags in CP110 gate clockMarcin Wojtas
Armada CP110 system controller comprises its own routine responsble for registering gate clocks. Among others 'flags' field in struct clk_init_data was not set, using a random values, which may cause an unpredicted behavior. This patch fixes the problem by resetting all fields of clk_init_data before assigning values for all gated clocks of Armada 7k/8k SoCs family. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21clk: nxp: clk-lpc32xx: Unmap region obtained by of_iomapArvind Yadav
Free memory mapping, if lpc32xx_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21clk: mvebu: Add clk support for the orion5x SoC mv88f5181Jamie Lentin
Referring to the u-boot sources for the Netgear WNR854T, add support for the mv88f5181. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin <jm@lentin.co.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-09-21clk: mediatek: clk-mt8173: Unmap region obtained by of_iomapArvind Yadav
Free memory mapping if init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-20clk: sunxi-ng: Fix reset offset for the A23 and A33Maxime Ripard
There's been a copy and paste mistake in the A23 and A33 from the H3, leading in the reset offset for the UART and I2C. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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