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path: root/drivers/clk
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2023-04-09clk: imx: imx8ulp: Add divider closest support to get more accurate clock rateJacky Bai
If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parentsPeng Fan
XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get wrong clock rate. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx93: Add nic and A55 clkPeng Fan
The A55 clock logic as below: A55_PLL ----------------->\ A55_SEL-->A55_CORE A55_CCM_ROOT--->A55_GATE->/ Add A55 CPU clk to support freq change. Add NIC CLK to reflect the clk status Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx93: add mcore_booted module paratemterPeng Fan
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX93, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and LPCG (clock gating) to gate clocks to peripherals. As below: anatop->ccm->lpcg->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for LPCG and CCM, auxiliary core normally only use LPCG hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: Add 300MHz freq support for imx9Jacky Bai
Add 300MHz frequency config support on i.MX93 PLL. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: support integer pllPeng Fan
The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: disable hardware select controlPeng Fan
When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: fix the rate tablePeng Fan
The Fvco should be range 2.4GHz to 5GHz, the original table voilate the spec, so update the table to fix it. Fixes: c196175acdd3 ("clk: imx: clk-fracn-gppll: Add more freq config for video pll") Fixes: 044034efbeea ("clk: imx: clk-fracn-gppll: fix mfd value") Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-criticalHaibo Chen
The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8mp: Add LDB root clockLiu Ying
This patch adds "media_ldb_root_clk" clock for the LDB in the MEDIAMIX subsystem. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8mp: correct DISP2 pixel clock typePeng Fan
The MEDIA_DISP2_CLK_ROOT use ccm_ahb_channel, it is bus type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403094633.3366446-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-07clk: qcom: Add Global Clock Controller driver for IPQ9574Devi Priya
Add Global Clock Controller (GCC) driver for ipq9574 based devices Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com
2023-04-07clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait valueKonrad Dybcio
Configure the disable wait value on the CX GDSC to ensure we don't get any undefined behavior. This was omitted when first adding the driver. Fixes: 8397e24278b3 ("clk: qcom: Add GPU clock controller driver for SM6375") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org
2023-04-07clk: qcom: gcc-sm6115: Mark RCGs shared where applicableKonrad Dybcio
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org
2023-04-05clk: rockchip: Remove values for mmask and nmask in struct ↵Christophe JAILLET
clk_fractional_divider Now that fractional_divider clk computes mmask and nmask when needed, there is no more need to provide them explicitly anymore. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/58e1950566e40e2fbb31004baee57a164ca6a390.1680423909.git.christophe.jaillet@wanadoo.fr Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-05clk: imx: Remove values for mmask and nmask in struct clk_fractional_dividerChristophe JAILLET
Now that fractional_divider clk computes mmask and nmask when needed, there is no more need to provide them explicitly anymore. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/187a2266c3a034a593a151d6e5e6b21118043b5d.1680423909.git.christophe.jaillet@wanadoo.fr Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-05clk: Compute masks for fractional_divider clk when needed.Christophe JAILLET
There is no real need to pre-compute mmask and nmask when handling fractional_divider clk. They can be computed when needed. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/0fd6357242c974259c9e034c6e28a0391c480bf0.1680423909.git.christophe.jaillet@wanadoo.fr Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-05clk: starfive: Add StarFive JH7110 always-on clock driverEmil Renner Berthing
Add driver for the StarFive JH7110 always-on clock controller and register an auxiliary device for always-on reset controller which is named as "rst-aon". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Add StarFive JH7110 system clock driverEmil Renner Berthing
Add driver for the StarFive JH7110 system clock controller and register an auxiliary device for system reset controller which is named as "rst-sys". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Rename "jh7100" to "jh71x0" for the common codeEmil Renner Berthing
Rename some variables from "jh7100" or "JH7100" to "jh71x0" or "JH71X0". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.hEmil Renner Berthing
Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making the code to be common. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Factor out common JH7100 and JH7110 codeEmil Renner Berthing
The clock control registers on the StarFive JH7100 and JH7110 work identically, so factor out the code then drivers for the two SoCs can share it without depending on each other. No functional change. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEHal Feng
Using ARCH_FOO symbol is preferred than SOC_FOO. Set obj-y for starfive/ in Makefile, so the StarFive drivers can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-04clk: qcom: dispcc-qcm2290: Add MDSS_CORE resetKonrad Dybcio
Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316-topic-qcm_dispcc_reset-v1-2-dd3708853014@linaro.org
2023-04-04clk: mediatek: Use right match table, include mod_devicetableStephen Boyd
This is copy/pasta that breaks modular builds. Fix the match table to use the right pointer, or the right device table type. And while we're including the header, fix the order to be linux, dt-bindings, and finally local. Cc: Garmin.Chang <Garmin.Chang@mediatek.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: f42b9e9a43e3 ("clk: mediatek: Add MT8188 wpesys clock support") Fixes: 0d2f2cefba64 ("clk: mediatek: Add MT8188 adsp clock support") Fixes: e4aaa60eae16 ("clk: mediatek: Add MT8188 vdosys0 clock support") Fixes: cfa4609f9bbe ("clk: mediatek: Add MT8188 vdosys1 clock support") Fixes: bb87c1109ce2 ("clk: mediatek: Add MT8188 vencsys clock support") Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304011039.UBDX1UOT-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304020649.QO2HlpD5-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304021055.WDhQPcoS-lkp@intel.com/ Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230404204553.1256263-1-sboyd@kernel.org
2023-04-03clk: stm32h7: Remove an unused field in struct stm32_fractional_dividerChristophe JAILLET
'mmask' has never been used in this driver. Remove it. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/e08a470fbd6151ebd83a548714c08807a80a8ad0.1680364296.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-03clk: imx: drop duplicated macroPeng Fan
Drop duplicated macro definition Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403082728.3199849-1-peng.fan@oss.nxp.com
2023-03-31clk: mediatek: Add MT8188 adsp clock supportGarmin.Chang
Add MT8188 adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-20-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 imp i2c wrapper clock supportGarmin.Chang
Add MT8188 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-19-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 wpesys clock supportGarmin.Chang
Add MT8188 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-18-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 vppsys1 clock supportGarmin.Chang
Add MT8188 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-17-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 vppsys0 clock supportGarmin.Chang
Add MT8188 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-16-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 vencsys clock supportGarmin.Chang
Add MT8188 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-15-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 vdosys1 clock supportGarmin.Chang
Add MT8188 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-14-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 vdosys0 clock supportGarmin.Chang
Add MT8188 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-13-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 vdecsys clock supportGarmin.Chang
Add MT8188 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-12-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 mfgcfg clock supportGarmin.Chang
Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-11-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 ipesys clock supportGarmin.Chang
Add MT8188 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-10-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 imgsys clock supportGarmin.Chang
Add MT8188 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-9-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 ccusys clock supportGarmin.Chang
Add MT8188 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-8-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 camsys clock supportGarmin.Chang
Add MT8188 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-7-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 infrastructure clock supportGarmin.Chang
Add MT8188 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-6-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 peripheral clock supportGarmin.Chang
Add MT8188 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-5-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 topckgen clock supportGarmin.Chang
Add MT8188 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-4-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: mediatek: Add MT8188 apmixedsys clock supportGarmin.Chang
Add MT8188 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-31clk: imx: clk-gpr-mux: Provide clock name in error messageStefan Wahren
In error case the error message doesn't provide much context: imx:clk-gpr-mux: failed to get parent (-EINVAL) So additionally provide the clock name in the message, in order to simplify the further analyze. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230308184603.10049-1-stefan.wahren@i2se.com
2023-03-31clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rateAdam Ford
By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-5-aford173@gmail.com
2023-03-31clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rateAdam Ford
By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-4-aford173@gmail.com
2023-03-31clk: imx: Add imx8m_clk_hw_composite_flags macroAdam Ford
In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-3-aford173@gmail.com
2023-03-31clk: imx: composite-8m: Add support to determine_rateAdam Ford
Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-2-aford173@gmail.com
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 13:59:22 +0000