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2021-01-12clk: qcom: gcc-sc7180: Mark the camera abh clock always ONTaniya Das
The camera clock controller requires the AHB clock, the driver when moved to use the pm_runtime_get() API, the camera ahb clock failed turn on before access, thus mark it as always ON. Reported-by: Stephen Boyd <sboyd@kernel.org> Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1608573816-1465-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-12clk: tegra30: Add hda clock default rates to clock driverPeter Geis
Current implementation defaults the hda clocks to clk_m. This causes hda to run too slow to operate correctly. Fix this by defaulting to pll_p and setting the frequency to the correct rate. This matches upstream t124 and downstream t30. Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ion Agorria <ion@agorria.com> Acked-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210108135913.2421585-2-pgwipeout@gmail.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
2021-01-12clk: renesas: r8a779a0: Add SYS-DMAC clocksGeert Uytterhoeven
Add the module clocks used by the Direct Memory Access Controller for System (SYS-DMAC) instances on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210107180109.1946475-1-geert+renesas@glider.be
2021-01-12clk: renesas: r8a779a0: Add SDHI supportWolfram Sang
We use the shiny new CPG library for that. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: rcar-gen3: Factor out CPG libraryWolfram Sang
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock handling and hook it to the generic Gen3 CPG driver so we have an equal state. V3U will make use of it in the next patch then. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clockWolfram Sang
We want to reuse SD clock handling for other SoCs and, thus, need to generalize it. So, don't access cpg_quirks in that realm. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: r8a779a0: Add MSIOF clocksGeert Uytterhoeven
Add the module clocks used by the Clock-Synchronized Serial Interface with FIFO (MSIOF) instances on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117090329.2128904-3-geert+renesas@glider.be
2021-01-12clk: renesas: r8a779a0: Add PFC/GPIO clocksGeert Uytterhoeven
Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks, and their parent clock CP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201019120614.22149-4-geert+renesas@glider.be
2021-01-07clk: renesas: r8a779a0: Fix parent of CBFUSA clockGeert Uytterhoeven
According to Figure 8.1.1 ("Block Diagram of CPG (R-Car V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of the CBFUSA clock is EXTAL. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201019120614.22149-3-geert+renesas@glider.be
2021-01-07clk: renesas: r8a779a0: Remove non-existent S2 clockGeert Uytterhoeven
The S2 internal core clock does not exist on R-Car V3U. Remove it. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201019120614.22149-2-geert+renesas@glider.be
2021-01-07clk: renesas: r8a779a0: Add HSCIF supportWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201228112715.14947-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-06clk: sunxi-ng: h6: Fix CEC clockAndre Przywara
The CEC clock on the H6 SoC is a bit special, since it uses a fixed pre-dividier for one source clock (the PLL), but conveys the other clock (32K OSC) directly. We are using a fixed predivider array for that, but fail to use the right flag to actually activate that. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Reported-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210106143246.11255-1-andre.przywara@arm.com
2021-01-06clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and resetSamuel Holland
While no information about the H6 RSB controller is included in the datasheet or manual, the vendor BSP and power management blob both reference the RSB clock parent and register address. These values were verified by experimentation. Since this clock/reset are added late, the specifier is added at the end to maintain the existing DT binding. The code is kept in register order. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-01-05memory: tegra124-emc: Make driver modularDmitry Osipenko
Add modularization support to the Tegra124 EMC driver, which now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module. Hence add a prepare/complete callbacks. similarly to what is done for the Tegra20/30 EMC drivers. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystemsLiu Ying
This patch adds some SCU clocks support for i.MX8qxp MIPI-LVDS subsystems. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()Liu Ying
This patch corrects display clocks for i.MX8qxp DC0 subsystem by calling imx_clk_scu2() to register them, instead of calling imx_clk_scu(). The reason is that the clocks can source from various parents. The clock source selection is controlled by Distributed Slave System Controller(DSC). According to the DSC spec, the below table describes the generic source selections for clocks with the same type in various subsystems. And, the display controller subsystem spec says the display clocks can source from PLL1, PLL2 or bypass clock, thus we may specify the correct parents for imx_clk_scu2(). The bypass clock's parent is determined by the SCU firmware. Currently, the parent is 'pixel_link_clk_in' from HW point of view. To be more specific, the parent is dummy for i.MX8qxp DC0, while HDMI TX PHY PLL for i.MX8qm DC0. In practice, the display clocks source from the bypass clock only when driving i.MX8qm HDMI TX. So, for the both display clocks, we simply specify 'dc0_bypass0_clk' bypass clock as a valid parent. ----------------------------------------- | src_sel[28:26] | | ----------------------------------------- | 0x0 | xtal24M | | 0x1 | PLL0 | | 0x2 | PLL1 | | 0x3 | PLL2 | | 0x4 | bypass reference clock | | 0x5 to 0x7 | reserved | ----------------------------------------- Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocksLiu Ying
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocksLiu Ying
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem PLL clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-04clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl
The XTAL clock is provided via .dts since Linux 5.6. Remove compatibility code for .dtbs which are older than that. The switch to the HHI syscon has been done with Linux 5.1. Also remove any code needed to support .dtbs that have not switched to the HHI syscon yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201221183624.932649-2-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl
Popagate the error code from meson_clk_pll_set_rate() when the PLL does not lock with the new settings. Fixes: 722825dcd54b2e ("clk: meson: migrate plls clocks to clk_regmap") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-4-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl
The error codes returned by meson_clk_get_pll_settings() are all negative. Make "ret" a signed integer in meson_clk_pll_set_rate() to make it match with the clk_ops.set_rate API as well as the data type returned by meson_clk_get_pll_settings(). Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-3-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate. Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try to switch from the new rate to the same rate again. Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-2-martin.blumenstingl@googlemail.com
2020-12-28clk: renesas: r8a779a0: Add RWDT clocksWolfram Sang
And introduce critical clocks, too, because RWDT is one. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201218173731.12839-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a779a0: Add VSPX clock supportKieran Bingham
Add clocks for the VSPX. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20201216151931.851547-4-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a779a0: Add VSPD clock supportKieran Bingham
Add clocks for the VSPD modules on the V3U. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20201216151931.851547-3-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a779a0: Add FCPVD clock supportKieran Bingham
Add clocks for the FCP for VSP-D module. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20201216151931.851547-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a77995: Add TMU clocksNiklas Söderlund
This patch adds TMU{0,1,2,3,4} clocks. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201209195343.803120-6-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a77990: Add TMU clocksNiklas Söderlund
This patch adds TMU{0,1,2,3,4} clocks. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201209195343.803120-5-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a77965: Add TMU clocksNiklas Söderlund
This patch adds TMU{0,1,2,3,4} clocks. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201209195343.803120-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a7796: Add TMU clocksNiklas Söderlund
This patch adds TMU{0,1,2,3,4} clocks. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201209195343.803120-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-21Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework got some nice improvements this time around. We gained the ability to get struct clk pointers from a struct clk_hw so that clk providers can consume the clks they provide, if they need to do something like that. This has been a long missing part of the clk provider API that will help us move away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are added for the clk_set_rate() "range" functions, similar to the tracepoints we already have for clk_set_rate() and we added a column to debugfs to help developers understand the hardware enable state of clks in case firmware or bootloader state is different than what is expected. Overall the core changes are mostly improving the clk driver writing experience. At the driver level, we have the usual collection of driver updates and new drivers for new SoCs. This time around the Qualcomm folks introduced a good handful of clk drivers for various parts of three or four SoCs. The SiFive folks added a new clk driver for their FU740 SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that for various new features. One last thing to note in the driver area is that the i.MX driver has gained a new binding to support SCU clks after being on the list for many months. It uses a two cell binding which is sort of rare in clk DT bindings. Beyond that we have the usual set of driver fixes and tweaks that come from more testing and finding out that some configuration was wrong or that a driver could support being built as a module. Summary: Core: - Add some trace points for clk_set_rate() "range" functions - Add hardware enable information to clk_summary debugfs - Replace clk-provider.h with of_clk.h when possible - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw New Drivers: - Bindings for Canaan K210 SoC clks - Support for SiFive FU740 PRCI - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs Updates: - DVFS support for AT91 clk driver - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors in Renesas clk drivers - One more conversion of DT bindings to json-schema - Make i.MX clk-gate2 driver more flexible - New two cell binding for i.MX SCU clks - Drop of_match_ptr() in i.MX8 clk drivers - Add arch dependencies for Rockchip clk drivers - Fix i2s on Rockchip rk3066 - Add MIPI DSI clks on Amlogic axg and g12 SoCs - Support modular builds of Amlogic clk drivers - Fix an Amlogic Video PLL clock dependency - Samsung Kconfig dependencies updates for better compile test coverage - Refactoring of the Samsung PLL clocks driver - Small Tegra driver cleanups - Minor fixes to Ingenic and VC5 clk drivers - Cleanup patches to remove unused variables and plug memory leaks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" clk: ingenic: Fix divider calculation with div tables clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 clk: si5351: Wait for bit clear after PLL reset clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error ...
2020-12-20Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and ↵Stephen Boyd
'clk-marvell' into clk-next - Bindings for Canaan K210 SoC clks * clk-ingenic: clk: ingenic: Fix divider calculation with div tables * clk-vc5: clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" * clk-cleanup: clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: bcm: dvp: Add MODULE_DEVICE_TABLE() clk: bcm: dvp: drop a variable that is assigned to only * clk-canaan: dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix * clk-marvell: clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
2020-12-20Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and ↵Stephen Boyd
'clk-silabs' into clk-next - Add some trace points for clk_set_rate() "range" functions - DVFS support for AT91 clk driver * clk-ti: clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs clk: ti: Fix memleak in ti_fapll_synth_setup * clk-analog: clk: axi-clkgen: move the OF table at the bottom of the file clk: axi-clkgen: wrap limits in a struct and keep copy on the state object dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format * clk-trace: clk: Trace clk_set_rate() "range" functions * clk-at91: clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error * clk-silabs: clk: si5351: Wait for bit clear after PLL reset
2020-12-20Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and ↵Stephen Boyd
'clk-summary' into clk-next - Support for SiFive FU740 PRCI - Add hardware enable information to clk_summary debugfs * clk-tegra: clk: tegra: Fix duplicated SE clock entry clk: tegra: bpmp: Clamp clock rates on requests clk: tegra: Do not return 0 on failure * clk-imx: (24 commits) clk: imx: scu: remove the calling of device_is_bound clk: imx: scu: Make pd_np with static keyword clk: imx8mq: drop of_match_ptr from of_device_id table clk: imx8mp: drop of_match_ptr from of_device_id table clk: imx8mn: drop of_match_ptr from of_device_id table clk: imx8mm: drop of_match_ptr from of_device_id table clk: imx: gate2: Remove unused variable ret clk: imx: gate2: Add locking in is_enabled op clk: imx: gate2: Add cgr_mask for more flexible number of control bits clk: imx: gate2: Check if clock is enabled against cgr_val clk: imx: gate2: Keep the register writing in on place clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case clk: imx: scu: fix build break when compiled as modules clk: imx: remove redundant assignment to pointer np clk: imx: remove unneeded semicolon clk: imx: lpcg: add suspend/resume support clk: imx: clk-imx8qxp-lpcg: add runtime pm support clk: imx: lpcg: allow lpcg clk to take device pointer clk: imx: imx8qxp-lpcg: add parsing clocks from device tree clk: imx: scu: add suspend/resume support ... * clk-sifive: clk: sifive: Add clock enable and disable ops clk: sifive: Fix the wrong bit field shift clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: sifive: Use common name for prci configuration clk: sifive: Extract prci core to common base dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI * clk-mediatek: clk: mediatek: Make mtk_clk_register_mux() a static function * clk-summary: clk: Add hardware-enable column to clk summary
2020-12-20Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and ↵Stephen Boyd
'clk-unused' into clk-next - Replace clk-provider.h with of_clk.h when possible * clk-amlogic: clk: meson: g12a: add MIPI DSI Host Pixel Clock dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings clk: meson: enable building as modules clk: meson: Kconfig: fix dependency for G12A clk: meson: axg: add MIPI DSI Host clock clk: meson: axg: add Video Clocks dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding dt-bindings: clk: axg-clkc: add Video Clocks * clk-rockchip: clk: rockchip: fix i2s gate bits on rk3066 and rk3188 clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks clk: rockchip: Remove redundant null check before clk_prepare_enable clk: rockchip: Add appropriate arch dependencies * clk-of: xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h> sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h> * clk-freescale: clk: fsl-flexspi: new driver dt-bindings: clock: document the fsl-flexspi-clk device clk: divider: add devm_clk_hw_register_divider_table() clk: qoriq: provide constants for the type clk: fsl-sai: use devm_clk_hw_register_composite_pdata() clk: composite: add devm_clk_hw_register_composite_pdata() clk: fsl-sai: fix memory leak clk: qoriq: Add platform dependencies * clk-unused: clk: scpi: mark scpi_clk_match as maybe unused clk: pwm: drop of_match_ptr from of_device_id table
2020-12-20Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', ↵Stephen Boyd
'clk-renesas' and 'clk-samsung' into clk-next - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw * clk-doc: clk: fix a kernel-doc markup * clk-qcom: (27 commits) clk: qcom: rpmh: add support for SM8350 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8350 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180 clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks clk: qcom: Add GDSC support for SDX55 GCC dt-bindings: clock: Add GDSC in SDX55 GCC clk: qcom: Add support for SDX55 RPMh clocks dt-bindings: clock: Introduce RPMHCC bindings for SDX55 clk: qcom: Add SDX55 GCC support dt-bindings: clock: Add SDX55 GCC clock bindings clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic" clk: qcom: rpmh: Add CE clock on sdm845. dt-bindings: clock: Add entry for crypto engine RPMH clock resource clk: qcom: dispcc-sm8250: handle MMCX power domain clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init() clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks dt-bindings: clock: Add support for LPASS Always ON Controller ... * clk-simplify: clk: remove unneeded dead-store initialization * clk-hw: clk: meson: g12: use devm variant to register notifiers clk: add devm variant of clk_notifier_register clk: meson: g12: drop use of __clk_lookup() clk: add api to get clk consumer from clk_hw clk: avoid devm_clk_release name clash * clk-renesas: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI * clk-samsung: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
2020-12-19clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"Geert Uytterhoeven
Commit 45c940184b501fc6 ("dt-bindings: clk: versaclock5: convert to yaml") accidentally changed "idt,voltage-microvolts" to "idt,voltage-microvolt" in the DT bindings, while the driver still used the former. Update the driver to match the bindings, as Documentation/devicetree/bindings/property-units.txt actually recommends using "microvolt". Fixes: 260249f929e81d3d ("clk: vc5: Enable addition output configurations of the Versaclock") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201218125253.3815567-1-geert+renesas@glider.be Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: ingenic: Fix divider calculation with div tablesPaul Cercueil
The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock. Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise. Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec
Two clock divider tables are missing sentinel at the end. Effect of that is that clock framework reads past the last entry. Fix that with adding sentinel at the end. Issue was discovered with KASan. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.net Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: s2mps11: Fix a resource leak in error handling paths in the probe functionChristophe JAILLET
Some resource should be released in the error handling path of the probe function, as already done in the remove function. The remove function was fixed in commit bf416bd45738 ("clk: s2mps11: Add missing of_node_put and of_clk_del_provider") Fixes: 7cc560dea415 ("clk: s2mps11: Add support for s2mps11") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20201212122818.86195-1-christophe.jaillet@wanadoo.fr Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9Terry Zhou
There is an error in the current code that the XTAL MODE pin was set to NB MPP1_31 which should be NB MPP1_9. The latch register of NB MPP1_9 has different offset of 0x8. Signed-off-by: Terry Zhou <bjzhou@marvell.com> [pali: Fix pin name in commit message] Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: si5351: Wait for bit clear after PLL resetSascha Hauer
Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits are self clearing bits, so wait until they are cleared before continuing. This fixes a case when the clock doesn't come up properly after a PLL reset. It worked properly when the frequency was below 900MHz, but with 900MHz it only works when we are waiting for the bit to clear. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20201130091033.1687-1-s.hauer@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: sam9x60: remove atmel,osc-bypass supportAlexandre Belloni
The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator bypass. Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver") Reported-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: sama7g5: register cpu clockClaudiu Beznea
Register CPU clock as being the master clock prescaler. This would be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the frequencies supported by SAMA7G5 could be directly received from CPUPLL + master clock prescaler and the extra divider would do no work in case it would be enabled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea
Re-factor master clock driver by splitting it into 2 clocks: prescaller and divider clocks. Based on registered clock flags the prescaler's rate could be changed at runtime. This is necessary for platforms supporting DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is also changed by DVFS to avoid over/under clocking of MCK0 consumers. The lower limit is changed to be able to set MCK0 accordingly by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea
MCK0 is changed at runtime by DVFS. Due to this, since not all IPs are glitch free aware at MCK0 changes, remove MCK0 from parent list of other clocks (e.g. generic clock, programmable/system clock, MCKX). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea
Allow runtime frequency changes for PLLs registered with proper flags. This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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