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path: root/drivers/clk/x86/clk-pmc-atom.c
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2017-07-18clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione
Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Darren Hart (VMware) <dvhart@infradead.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-05-01clk: x86: pmc-atom: Checking for IS_ERR() instead of NULLDan Carpenter
clkdev_hw_create() returns NULLs on error, it doesn't return error pointers. Fixes: 41ee7caf59e1 ("clk: x86: add "mclk" alias for Baytrail/Cherrytrail") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: x86: add "mclk" alias for Baytrail/CherrytrailPierre-Louis Bossart
Due to timing requirements, TI and Conexant manage the audio reference clock from their ASoC codec drivers using the "mclk" string. This patch adds another lookup for the "pmc_plt_clk_3" clock to avoid Intel-specific tests in those codec drivers and use code as-is. To avoid a leak, clk_add_alias() is not used in this patch. Instead the lookup is created manually as part of the .probe() step and dropped in the .remove() step. "pmc_plt_clk_3" is used exclusively for audio on all known Baytrail/CherryTrail designs and is e.g. routed on the MCLK (pin 26) of the MinnowBoardMAX Turbot LSE connector. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: x86: Add Atom PMC platform clocksIrina Tirdea
The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them. Port from legacy by Pierre Bossart, integration in clock framework by Irina Tirdea Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>