Age | Commit message (Expand) | Author |
---|---|---|
2013-04-04 | clk: tegra: defer application of init table | Stephen Warren |
2013-04-04 | clk: tegra: Fix cdev1 and cdev2 IDs | Prashant Gaikwad |
2013-04-04 | clk: tegra: Make gr2d and gr3d clocks children of pll_c | Thierry Reding |
2013-04-04 | Merge branch 'for-3.10/soc' into for-3.10/clk | Stephen Warren |
2013-04-01 | clk: tegra: Allow PLLE training to succeed | Thierry Reding |
2013-03-11 | clk: tegra: No 7.1 super clk dividers on Tegra20 | Peter De Schrijver |
2013-03-04 | clk: Tegra: Remove duplicate smp_twd clock | Prashant Gaikwad |
2013-02-13 | clk: tegra: initialise parent of uart clocks | Laxman Dewangan |
2013-02-13 | clk: tegra: fix driver to match DT binding | Stephen Warren |
2013-02-12 | clk: tegra: Add missing spinlock for hclk and pclk | Peter De Schrijver |
2013-01-28 | clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops | Joseph Lo |
2013-01-28 | clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s | Prashant Gaikwad |
2013-01-28 | clk: tegra: add clock support for Tegra20 | Prashant Gaikwad |