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path: root/drivers/clk/qcom
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2022-12-06clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-7-dmitry.baryshkov@linaro.org
2022-12-06clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_namesDmitry Baryshkov
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-6-dmitry.baryshkov@linaro.org
2022-12-06clk: qcom: gcc-msm8974: move clock parent tables downDmitry Baryshkov
Rearrage clock parent tables and PLL declarations (pull parents down and gpll4 up), so that we can use pll hw clock fields in the next commit. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-5-dmitry.baryshkov@linaro.org
2022-12-06clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-4-dmitry.baryshkov@linaro.org
2022-12-05clk: qcom: gcc-ipq4019: switch to devm_clk_notifier_registerRobert Marko
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221205113545.575702-1-robert.marko@sartura.hr
2022-12-02clk: qcom: rpmh: remove usage of platform nameDmitry Baryshkov
Now that all clocks have individual names, remove the names of SoCs from the RPMH clock definitions. Replace it with the common clk_rpmh_ prefix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-9-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: rename VRM clock dataDmitry Baryshkov
RPMH VRM clocks are frequently shared between several platforms. It makes little sense to encode the SoC name into the clock name, if the same clock is used for other SoCs. Rework the VRM clock definitions to add resource-specific suffix. Keep the userspace-visible clock name, but encode the part of cmd resource and the divider into the variable name. This also make it obvious which variant is used, making the code less error-prone. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-8-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: rename ARC clock dataDmitry Baryshkov
RPMH ARC clocks are frequently shared between several platforms. It makes little sense to encode the SoC name into the clock name, if the same clock is used for other SoCs. Rework the ARC clock definitions to remove the SoC name. Keep the userspace-visible clock name, but encode the divider into the variable name. This also makes it obvious which divider is used by the platform, making the code less error-prone. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-7-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: support separate symbol name for the RPMH clocksDmitry Baryshkov
Both ARC and VRM clocks have minor differences between platforms. However using SoC names directly results in duplication, confusion and occasional errors. Next patches are going to drop the SoC names and encode these differences into the clock names. To keep the system clock names (visible to userspace) intact, add separate symbol names that are used in the code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-6-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: remove platform names from BCM clocksDmitry Baryshkov
There are no platform-specific parts in the BCM clocks, drop the platform name from the clock definitions, replacing it with clk_rpmh to have the common prefix. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-5-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: drop all _ao namesDmitry Baryshkov
In preparation for the further cleanup, remove the active only names, they can be easily generated from the standard ones. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-4-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: reuse common duplicate clocksDmitry Baryshkov
After the grouping it is obvious that some of the clock definitions are pure duplicates. Rename them to use a single common name for the clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-3-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: group clock definitions togetherDmitry Baryshkov
In preparations to the further changes, group all RPMH clock definitions to ease review. Group the clocks by their type to make similar/duplicate clocks stand out. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-2-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: drop the platform from clock definitionsDmitry Baryshkov
A single clock definition can be used on different platforms. Thus the platform part of the clock name is not correct (and can be misleading). Remove the platform-specific part of the defined clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-5-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: drop the _clk suffix completelyDmitry Baryshkov
Drop the _clk suffix from other clocks too. This does not produce any user-visible changes, just syntax sugar. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-4-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: drop separate active-only namesDmitry Baryshkov
To simplify code reviews remove duplication between normal and active-only clock names. Get a single clock name and generate both names internally. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-3-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: remove unused active-only clock namesDmitry Baryshkov
The RPM_FIXED and RPM_XO_BUFFER clocks do not have the active-only counterparts. Drop corresponding unused arguments. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-2-dmitry.baryshkov@linaro.org
2022-12-01clk: qcom: Add GCC driver for SM8550Abel Vesa
Add Global Clock controller (GCC) driver for SM8550 SoC, which includes the gcc resets and gdsc. This patch is based on an initial downstream driver. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-6-abel.vesa@linaro.org
2022-12-01clk: qcom: Add LUCID_OLE PLL type for SM8550Abel Vesa
Add a LUCID_OLE PLL type for SM8550 SoC from Qualcomm. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-5-abel.vesa@linaro.org
2022-12-01clk: qcom: gdsc: Increase status poll timeoutAbel Vesa
The SM8550 GCC GDSCs need a higher timeout value when polling for status, so increase it to 1500us, while leaving the delay between disable-enable sequence for votable gdscs to stay the same. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-4-abel.vesa@linaro.org
2022-12-01clk: qcom: gcc-msm8939: Add rates to the GP clocksLin, Meng-Bo
Similar to msm8916, msm8939 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Reference: https://lore.kernel.org/r/20220612145955.385787-5-nikita@trvn.ru Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221117171343.24216-1-linmengbo0689@protonmail.com
2022-12-01clk: qcom: hfpll: use devm_platform_get_and_ioremap_resource()Minghao Chi
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/202211171403340042731@zte.com.cn
2022-12-01clk: qcom: ipq8074: populate fw_name for all parentsRobert Marko
It appears that having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for all parent clocks in parent_data. Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data") Co-developed-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
2022-12-01clk: qcom: krait-cc: convert to parent_data APIChristian Marangi
Modernize the krait-cc driver to parent-data API and refactor to drop any use of parent_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. .name is also declared to save compatibility with old DT. While at it also drop some hardcoded index and introduce an enum to make index values more clear. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
2022-12-01clk: qcom: krait-cc: convert to devm_clk_hw_registerChristian Marangi
clk_register is now deprecated. Convert the driver to devm_clk_hw_register. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
2022-12-01clk: qcom: krait-cc: handle secondary mux sourcing out of acpu_auxChristian Marangi
Some bootloader may leave the system in an even more undefined state with the secondary mux of L2 or other cores sourcing out of the acpu_aux parent. This results in the clk set to the PXO rate or a PLL8 rate. The current logic to reset the mux and set them to a defined state only handle if the mux are configured to source out of QSB. Change this and force a new and defined state if the current clk is lower than the aux rate. This way we can handle any wrong configuration where the mux is sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1), PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz). Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
2022-12-01clk: qcom: krait-cc: also enable secondary mux and div clkChristian Marangi
clk-krait ignore any rate change if clk is not flagged as enabled. Correctly enable the secondary mux and div clk to correctly change rate instead of silently ignoring the request. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
2022-12-01clk: qcom: krait-cc: fix wrong parent order for secondary muxChristian Marangi
The secondary mux parent order is swapped. This currently doesn't cause problems as the secondary mux is used for idle clk and as a safe clk source while reprogramming the hfpll. Each mux have 2 or more output but he always have a safe source to switch while reprogramming the connected pll. We use a clk notifier to switch to the correct parent before clk core can apply the correct rate. The parent to switch is hardcoded in the mux struct. For the secondary mux the safe source to use is the qsb parent as it's the only fixed clk as the acpus_aux is a pll that can source from pxo or from pll8. The hardcoded safe parent for the secondary mux is set to index 0 that in the secondary mux map is set to 2. But the index 0 is actually acpu_aux in the parent list. Fix the swapped parents to correctly handle idle frequency and output a sane clk_summary report. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
2022-12-01clk: qcom: krait-cc: use devm variant for clk notifier registerChristian Marangi
Use devm variant for clk notifier register and correctly handle free resource on driver remove. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
2022-12-01clk: qcom: clk-krait: fix wrong div2 functionsChristian Marangi
Currently div2 value is applied to the wrong bits. This is caused by a bug in the code where the shift is done only for lpl, for anything else the mask is not shifted to the correct bits. Fix this by correctly shift if lpl is not supported. Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108215625.30186-1-ansuelsmth@gmail.com
2022-12-01clk: qcom: kpss-xcc: register it as clk providerChristian Marangi
krait-cc use this driver for the secondary mux. Register it as a clk provider to correctly use this clk in other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
2022-12-01clk: qcom: ipq8074: add missing networking resetsRobert Marko
Downstream QCA 5.4 kernel defines networking resets which are not present in the mainline kernel but are required for the networking drivers. So, port the downstream resets and avoid using magic values for mask, construct mask for resets which require multiple bits to be set/cleared. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
2022-12-01clk: qcom: reset: support resetting multiple bitsRobert Marko
This patch adds the support for giving the complete bitmask in reset structure and reset operation will use this bitmask for all reset operations. Currently, reset structure only takes a single bit for each reset and then calculates the bitmask by using the BIT() macro. However, this is not sufficient anymore for newer SoC-s like IPQ8074, IPQ6018 and more, since their networking resets require multiple bits to be asserted in order to properly reset the HW block completely. So, in order to allow asserting multiple bits add "bitmask" field to qcom_reset_map, and then use that bitmask value if its populated in the driver, if its not populated, then we just default to existing behaviour and calculate the bitmask on the fly. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
2022-12-01clk: qcom: lpass-sc7180: Avoid an extra "struct dev_pm_ops"Douglas Anderson
The two devices managed by lpasscorecc-sc7180.c each had their own "struct dev_pm_ops". This is not needed. They are exactly the same and the structure is "static const" so it can't possible change. combine the two. This matches what's done for sc7280. This should be a noop other than saving a few bytes. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104064055.3.I90ba14a47683a484f26531a08f7b46ace7f0a8a9@changeid
2022-12-01clk: qcom: lpass-sc7180: Fix pm_runtime usageDouglas Anderson
The sc7180 lpass clock controller's pm_runtime usage wasn't broken quite as spectacularly as the sc7280's pm_runtime usage, but it was still broken. Putting some printouts in at boot showed me this (with serial console enabled, which makes the prints slow and thus changes timing): [ 3.109951] DOUG: my_pm_clk_resume, usage=1 [ 3.114767] DOUG: my_pm_clk_resume, usage=1 [ 3.664443] DOUG: my_pm_clk_suspend, usage=0 [ 3.897566] DOUG: my_pm_clk_suspend, usage=0 [ 3.910137] DOUG: my_pm_clk_resume, usage=1 [ 3.923217] DOUG: my_pm_clk_resume, usage=0 [ 4.440116] DOUG: my_pm_clk_suspend, usage=-1 [ 4.444982] DOUG: my_pm_clk_suspend, usage=0 [ 14.170501] DOUG: my_pm_clk_resume, usage=1 [ 14.176245] DOUG: my_pm_clk_resume, usage=0 ...or this w/out serial console: [ 0.556139] DOUG: my_pm_clk_resume, usage=1 [ 0.556279] DOUG: my_pm_clk_resume, usage=1 [ 1.058422] DOUG: my_pm_clk_suspend, usage=-1 [ 1.058464] DOUG: my_pm_clk_suspend, usage=0 [ 1.186250] DOUG: my_pm_clk_resume, usage=1 [ 1.186292] DOUG: my_pm_clk_resume, usage=0 [ 1.731536] DOUG: my_pm_clk_suspend, usage=-1 [ 1.731557] DOUG: my_pm_clk_suspend, usage=0 [ 10.288910] DOUG: my_pm_clk_resume, usage=1 [ 10.289496] DOUG: my_pm_clk_resume, usage=0 It seems to be doing roughly the right sequence of calls, but just like with sc7280 this is more by luck than anything. Having a usage of -1 is just not OK. Let's fix this like we did with sc7280. Signed-off-by: Douglas Anderson <dianders@chromium.org> Fixes: ce8c195e652f ("clk: qcom: lpasscc: Introduce pm autosuspend for SC7180") Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104064055.2.I49b25b9bda9430fc7ea21e5a708ca5a0aced2798@changeid
2022-12-01clk: qcom: lpass-sc7280: Fix pm_runtime usageDouglas Anderson
The pm_runtime usage in lpass-sc7280 was broken in quite a few ways. Specifically: 1. At the end of probe it called "put" twice. This is a no-no and will end us up with a negative usage count. Even worse than calling "put" twice, it never called "get" once. Thus after bootup it could be seen that the runtime usage of the devices managed by this driver was -2. 2. In some error cases it manually called pm_runtime_disable() even though it had previously used devm_add_action_or_reset() to set this up to be called automatically. This meant that in these error cases we'd double-call pm_runtime_disable(). 3. It forgot to call undo pm_runtime_use_autosuspend(), which can sometimes have subtle problems (and the docs specifically mention that you need to undo this function). Overall the above seriously calls into question how this driver is working. It seems like a combination of "it doesn't", "by luck", and "because of the weirdness of runtime_pm". Specifically I put a printout to the serial console every time the runtime suspend/resume was called for the two devices created by this driver (I wrapped the pm_clk calls). When I had serial console enabled, I found that the calls got resumed at bootup (when the clk core probed and before our double-put) and then never touched again. That's no good. [ 0.829997] DOUG: my_pm_clk_resume, usage=1 [ 0.835487] DOUG: my_pm_clk_resume, usage=1 When I disabled serial console (speeding up boot), I got a different pattern, which I guess (?) is better: [ 0.089767] DOUG: my_pm_clk_resume, usage=1 [ 0.090507] DOUG: my_pm_clk_resume, usage=1 [ 0.151885] DOUG: my_pm_clk_suspend, usage=-2 [ 0.151914] DOUG: my_pm_clk_suspend, usage=-2 [ 1.825747] DOUG: my_pm_clk_resume, usage=-1 [ 1.825774] DOUG: my_pm_clk_resume, usage=-1 [ 1.888269] DOUG: my_pm_clk_suspend, usage=-2 [ 1.888282] DOUG: my_pm_clk_suspend, usage=-2 These different patterns have to do with the fact that the core PM Runtime code really isn't designed to be robust to negative usage counts and sometimes may happen to stumble upon a behavior that happens to "work". For instance, you can see that __pm_runtime_suspend() will treat any non-zero value (including negative numbers) as if the device is in use. In any case, let's fix the driver to be correct. We'll hold a pm_runtime reference for the whole probe and then drop it (once!) at the end. We'll get rid of manual pm_runtime_disable() calls in the error handling. We'll also switch to devm_pm_runtime_enable(), which magically handles undoing pm_runtime_use_autosuspend() as of commit b4060db9251f ("PM: runtime: Have devm_pm_runtime_enable() handle pm_runtime_dont_use_autosuspend()"). While we're at this, let's also use devm_pm_clk_create() instead of rolling it ourselves. Note that the above changes make it obvious that lpassaudio_create_pm_clks() was doing more than just creating clocks. It was also setting up pm_runtime parameters. Let's rename it. All of these problems were found by code inspection. I started looking at this driver because it was involved in a deadlock that I reported a while ago [1]. Though I bisected the deadlock to commit 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support"), it was never really clear why that patch affected it other than a luck of timing changes. I'll also note that by fixing the timing (as done in this change) we also seem to aboid the deadlock, which is a nice benefit. Also note that some of the fixes here are much the same type of stuff that Dmitry did in commit 72cfc73f4663 ("clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create"), but I guess lpassaudiocc-sc7280.c didn't exist then. [1] https://lore.kernel.org/r/20220922154354.2486595-1-dianders@chromium.org Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104064055.1.I00a0e4564a25489e85328ec41636497775627564@changeid
2022-11-22clk: qcom: gcc-sc8280xp: add cxo as parent for three ufs ref clksShazad Hussain
The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for two PHYs are all sourced from CXO. Added parent_data for all three reference clocks described above to reflect that all three clocks are sourced from CXO to have valid frequency for the ref clock needed by UFS controller driver. Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%2FW@hovoldconsulting.com/ Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20221115152956.21677-1-quic_shazhuss@quicinc.com Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-11-15clk: qcom: Add display clock controller driver for SM6375Konrad Dybcio
Add support for the display clock controller found on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115155808.10899-2-konrad.dybcio@linaro.org
2022-11-09clk: qcom: Add SC8280XP display clock controllerBjorn Andersson
The Qualcomm SC8280XP platform has two display clock controller instances, add support for these. Duplication between the two implementations is reduced by reusing any constant data between the two sets of clock data. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926203800.16771-3-quic_bjorande@quicinc.com
2022-11-07clk: qcom: ipq8074: convert to parent dataRobert Marko
Convert the IPQ8074 GCC driver to use parent data instead of global name matching. Utilize ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
2022-11-07clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocksMelody Olvera
Add support for RMPh clocks for QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190441.4002212-5-quic_molvera@quicinc.com
2022-11-05clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150Robert Foss
SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-6-robert.foss@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350Robert Foss
SM8350 supports embedded displayport, but the clocks for this were previously not accounted for. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-5-robert.foss@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdscRobert Foss
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-3-robert.foss@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350Robert Foss
SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-2-robert.foss@linaro.org
2022-11-05clk: qcom: gcc-sm8250: Use retention mode for USB GDSCsManivannan Sadhasivam
USB controllers on SM8250 doesn't work after coming back from suspend. This can be fixed by keeping the USB GDSCs in retention mode so that hardware can keep them ON and put into rentention mode once the parent domain goes to a low power state. Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102091320.66007-1-manivannan.sadhasivam@linaro.org
2022-11-05clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte srcKonrad Dybcio
Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to ensure set_rate can succeed. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010155546.73884-1-konrad.dybcio@somainline.org
2022-11-05clk: qcom: gcc-sm6125: Remove gpll7 from sdcc2_appsMartin Botka
This removes gpll7 clock source from sdcc2_apps as it caused issues on the device during testing Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221001185431.493440-1-martin.botka@somainline.org
2022-11-05clk: qcom: gcc-ipq806x: use parent_data for the last remaining entryDmitry Baryshkov
Use parent_data for the last remaining entry (pll4). This clock is provided by the lcc device. Fixes: cb02866f9a74 ("clk: qcom: gcc-ipq806x: convert parent_names to parent_data") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927113826.246241-3-dmitry.baryshkov@linaro.org
2022-11-04clk: qcom: gdsc: Remove direct runtime PM callsStephen Boyd
We shouldn't be calling runtime PM APIs from within the genpd enable/disable path for a couple reasons. First, this causes an AA lockdep splat[1] because genpd can call into genpd code again while holding the genpd lock. WARNING: possible recursive locking detected 5.19.0-rc2-lockdep+ #7 Not tainted -------------------------------------------- kworker/2:1/49 is trying to acquire lock: ffffffeea0370788 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30 but task is already holding lock: ffffffeea03710a8 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&genpd->mlock); lock(&genpd->mlock); *** DEADLOCK *** May be due to missing lock nesting notation 3 locks held by kworker/2:1/49: #0: 74ffff80811a5748 ((wq_completion)pm){+.+.}-{0:0}, at: process_one_work+0x320/0x5fc #1: ffffffc008537cf8 ((work_completion)(&genpd->power_off_work)){+.+.}-{0:0}, at: process_one_work+0x354/0x5fc #2: ffffffeea03710a8 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30 stack backtrace: CPU: 2 PID: 49 Comm: kworker/2:1 Not tainted 5.19.0-rc2-lockdep+ #7 Hardware name: Google Lazor (rev3 - 8) with KB Backlight (DT) Workqueue: pm genpd_power_off_work_fn Call trace: dump_backtrace+0x1a0/0x200 show_stack+0x24/0x30 dump_stack_lvl+0x7c/0xa0 dump_stack+0x18/0x44 __lock_acquire+0xb38/0x3634 lock_acquire+0x180/0x2d4 __mutex_lock_common+0x118/0xe30 mutex_lock_nested+0x70/0x7c genpd_lock_mtx+0x24/0x30 genpd_runtime_suspend+0x2f0/0x414 __rpm_callback+0xdc/0x1b8 rpm_callback+0x4c/0xcc rpm_suspend+0x21c/0x5f0 rpm_idle+0x17c/0x1e0 __pm_runtime_idle+0x78/0xcc gdsc_disable+0x24c/0x26c _genpd_power_off+0xd4/0x1c4 genpd_power_off+0x2d8/0x41c genpd_power_off_work_fn+0x60/0x94 process_one_work+0x398/0x5fc worker_thread+0x42c/0x6c4 kthread+0x194/0x1b4 ret_from_fork+0x10/0x20 Second, this confuses runtime PM on CoachZ for the camera devices by causing the camera clock controller's runtime PM usage_count to go negative after resuming from suspend. This is because runtime PM is being used on the clock controller while runtime PM is disabled for the device. The reason for the negative count is because a GDSC is represented as a genpd and each genpd that is attached to a device is resumed during the noirq phase of system wide suspend/resume (see the noirq suspend ops assignment in pm_genpd_init() for more details). The camera GDSCs are attached to camera devices with the 'power-domains' property in DT. Every device has runtime PM disabled in the late system suspend phase via __device_suspend_late(). Runtime PM is not usable until runtime PM is enabled in device_resume_early(). The noirq phases run after the 'late' and before the 'early' phase of suspend/resume. When the genpds are resumed in genpd_resume_noirq(), we call down into gdsc_enable() that calls pm_runtime_resume_and_get() and that returns -EACCES to indicate failure to resume because runtime PM is disabled for all devices. Upon closer inspection, calling runtime PM APIs like this in the GDSC driver doesn't make sense. It was intended to make sure the GDSC for the clock controller providing other GDSCs was enabled, specifically the MMCX GDSC for the display clk controller on SM8250 (sm8250-dispcc), so that GDSC register accesses succeeded. That will already happen because we make the 'dev->pm_domain' a parent domain of each GDSC we register in gdsc_register() via pm_genpd_add_subdomain(). When any of these GDSCs are accessed, we'll enable the parent domain (in this specific case MMCX). We also remove any getting of runtime PM during registration, because when a genpd is registered it increments the count on the parent if the genpd itself is already enabled. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Johan Hovold <johan+linaro@kernel.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Taniya Das <quic_tdas@quicinc.com> Cc: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Reported-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/CAE-0n52xbZeJ66RaKwggeRB57fUAwjvxGxfFMKOKJMKVyFTe+w@mail.gmail.com [1] Fixes: 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20221103183030.3594899-1-swboyd@chromium.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 13:53:38 +0000