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path: root/drivers/clk/meson/gxbb.c
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2018-02-12clk: meson: gxbb: add the fractional part of the fixed_pllJerome Brunet
The fixed_pll of gxbb and gxl also has a fractional parameter. This has not been a problem so far because the fractional part is actually set to 0 on these platforms, so the rate remains correct when it is ignored. Still, it is better represent the pll the way it is, so add the frac parameter now Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: fix rate calculation of plls with a fractional partJerome Brunet
The rate of the parent should not be multiplied by 2 when the pll has a fractional part. This is making the rate calculation of the gxl_hdmi_pll wrong (and others as well). This multiplication is specific to the hdmi_pll of gxbb and is most likely due to a multiplier sitting in front of this particular pll. Add a fixed factor clock in front on the gxbb pll and remove this constant from the calculation to fix the problem Fixes: 4a47295144dd ("clk: meson: fractional pll support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: add the gxl hdmi pllJerome Brunet
The hdmi pll used in the gxl family is actually different from the gxbb one. The register layout is completely different, which explain why the hdmi pll rate has always been rubbish on the gxl family. Adding the correct register field is the first part of the fix to get a correct rate out the hdmi pll Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: add od3 to the pll driverJerome Brunet
Some meson plls, such as the hdmi pll, are using a 3rd od parameter, which is yet another "power of 2" post divider. Add it to fix the calculation of the hdmi_pll rate Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: remove useless pll rate params tablesJerome Brunet
Read-only plls don't need param table to recalculate the rate. Providing them with a param table is just a waste of memory. Remove the useless tables from sys_pll on gxbb and axg. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-14clk: meson: make the spinlock naming more specificYixun Lan
Make the spinlock more specific, so better for lockdep debugging and ctags/grep. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-08clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocksJerome Brunet
Remove CLK_IGNORE_UNUSED from mmc clocks. This was only needed while the mmc driver incorrectly used the xtal as source instead of the mmc clock. Now, the driver takes the correct clock, CCF is aware that the clock is being used and we can remove this flag. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com>
2017-11-27clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan
According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl-s905x-p212 board. The following published datasheets are wrong and should be updated [1] GXBB v1.1.4 [2] GXL v0.3_20170314 Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-10-20clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong
The Amlogic Meson GX SoCs needs these two clocks to power up the VPU power domain. These two clocks are similar to the MALI clocks by having a glitch-free mux and two similar clocks with gate, divider and muxes. Acked-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: removed the CLK_IGNORE_UNUSED on muxes and dividers] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-23Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into ↵Stephen Boyd
clk-next Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet
Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix protection against undefined clksJerome Brunet
gxbb clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: a70c6e06ed7c ("clk: meson: gxbb: protect against holes in the onecell_data array") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-06-16Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd
clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
2017-06-16clk: meson: gxbb: add all clk81 parentsJerome Brunet
Remove the FIXME on clk81 mux and add all the documented parents Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-02clk: meson-gxbb: Add const to some parent name arraysStephen Boyd
These can be marked as const * const. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-05-29clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong
On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet
clk81 already has CLK_IS_CRITICAL so CLK_IGNORE_UNUSED is not necessary Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-29clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl
It seems that the "cpu_clk" was carried over from the meson8b clock controller driver. On Meson GX (GXBB/GXL/GXM) the registers which are used by the cpu_clk have a different purpose (in other words: they don't control the CPU clock anymore). HHI_SYS_CPU_CLK_CNTL1 bits 31:24 are reserved according to the public S905 datasheet, while bit 23 is the "A53_trace_clk_DIS" gate (which according to the datasheet should only be used in case a silicon bug is discovered) and bits 22:20 are a divider (A53_trace_clk). The meson clk-cpu code however expects that bits 28:20 are reserved for a divider (according to the public S805 datasheet this "SCALE_DIV: This value represents an N+1 divider of the input clock."). The CPU clock on Meson GX SoCs is provided by the SCPI DVFS clock driver instead. Two examples from a Meson GXL S905X SoC: - vcpu (SCPI DVFS clock 0) rate: 1000000000 / cpu_clk rate: 708000000 - vcpu (SCPI DVFS clock 0) rate: 1512000000 / cpu_clk rate: 708000000 Unfortunately the CLKID_CPUCLK was already exported (but is currently not used) to DT. Due to the removal of this clock definition there is now a hole in the clk_hw_onecell_data (which is not a problem because this case is already handled in gxbb_clkc_probe). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-07clk: meson: gxbb: add cts_i958 clockJerome Brunet
This adds the cts_i958 clock to control the clock source of the spdif output block. This mux is not explicitly mentionned in the documentation but it is critical to the spdif dai. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer) Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-07clk: meson: gxbb: add cts_mclk_i958Jerome Brunet
Add the spdif master clock also referred as cts_mclk_i958 Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-07clk: meson: gxbb: add cts_amclkJerome Brunet
Add the i2s master clock also referred as cts_amclk Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-07clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet
The clock controller is getting more complex and it might be possible, in the future, to have holes in the clk_hw_onecell_data array. Just make sure we skip those holes if it ever happens. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-04clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong
The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM SoCs embeds a different GP0 PLL, and needs different parameters with a vendor provided reduced rate table. This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order to use the GXL GP0 PLL instead of the GXBB specific one. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong
Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be initializated in the the GP0 control registers before configuring the rate with the rate table provided parameters. GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-3-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Add MALI clocksNeil Armstrong
The Mali is clocked by two identical clock paths behind a glitch free mux to safely change frequency while running. The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. Expose these two clocks trees using generic clocks. Finally the glitch free mux is added as "mali" clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-3-git-send-email-narmstrong@baylibre.com
2017-03-27clk: meson: gxbb: mpll: use rw operationJerome Brunet
Use read/write operations for the mpll clocks instead of the read-only ones. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-7-jbrunet@baylibre.com
2017-03-27clk: meson: mpll: add rw operationJerome Brunet
This patch adds new callbacks to the meson-mpll driver to control and set the pll rate. For this, we also need to add the enable bit and sdm enable bit. The corresponding parameters are added to mpll data structure. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com
2017-03-27clk: gxbb: put dividers and muxes in tablesJerome Brunet
Until now, there was only 2 dividers and 2 muxes declared for the gxbb platform. With the ongoing work on various subsystem, including audio, this is about to change. Use the same approach as gates for dividers and muxes, putting them in tables to fix the register address at runtime. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-5-jbrunet@baylibre.com
2017-03-27clk: meson: add missing const qualifiers on gate arraysJerome Brunet
Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-3-jbrunet@baylibre.com
2017-01-23clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-02Merge branch 'clk-meson-gxbb' into clk-nextMichael Turquette
2016-09-01gxbb: clk: Adjust MESON_GATE macro to be shared with meson8bAlexander Müller
The macro used gxbb_ prefix for clock definitions. In order to share the macro between gxbb and meson8b, the prefix must be moved to gxbb.c. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com
2016-08-15Merge branch 'clk-meson-gxbb' into clk-nextStephen Boyd
* clk-meson-gxbb: clk: gxbb: add MMC gate clocks, and expose for DT
2016-08-15clk: gxbb: add MMC gate clocks, and expose for DTKevin Hilman
Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: gxbb: use builtin_platform_driver to simplify the codeWei Yongjun
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-06clk: meson: make gxbb explicitly non-modularPaul Gortmaker
The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_GXBB drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE and ALIAS are no-op for non-modules. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-3-paul.gortmaker@windriver.com
2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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