summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2022-12-08riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich
Current implementation of update_mmu_cache function performs local TLB flush. It does not take into account ASID information. Besides, it does not take into account other harts currently running the same mm context or possible migration of the running context to other harts. Meanwhile TLB flush is not performed for every context switch if ASID support is enabled. Patch [1] proposed to add ASID support to update_mmu_cache to avoid flushing local TLB entirely. This patch takes into account other harts currently running the same mm context as well as possible migration of this context to other harts. For this purpose the approach from flush_icache_mm is reused. Remote harts currently running the same mm context are informed via SBI calls that they need to flush their local TLBs. All the other harts are marked as needing a deferred TLB flush when this mm context runs on them. [1] https://lore.kernel.org/linux-riscv/20220821013926.8968-1-tjytimi@163.com/ Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Fixes: 65d4b9c53017 ("RISC-V: Implement ASID allocator") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/#t Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-12-08Merge tag 'soc-fixes-6.1-5' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fix from Arnd Bergmann: "One last build fix came in, addressing a link failure when building without CONFIG_OUTER_CACHE" * tag 'soc-fixes-6.1-5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: at91: fix build for SAMA5D3 w/o L2 cache
2022-12-08Merge tag 'loongarch-fixes-6.1-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson Pull LoongArch fixes from Huacai Chen: "Export smp_send_reschedule() for modules use, fix a huge page entry update issue, and add documents for booting description" * tag 'loongarch-fixes-6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: docs/zh_CN: Add LoongArch booting description's translation docs/LoongArch: Add booting description LoongArch: mm: Fix huge page entry update for virtual machine LoongArch: Export symbol for function smp_send_reschedule()
2022-12-08arm64: efi: Recover from synchronous exceptions occurring in firmwareArd Biesheuvel
Unlike x86, which has machinery to deal with page faults that occur during the execution of EFI runtime services, arm64 has nothing like that, and a synchronous exception raised by firmware code brings down the whole system. With more EFI based systems appearing that were not built to run Linux (such as the Windows-on-ARM laptops based on Qualcomm SOCs), as well as the introduction of PRM (platform specific firmware routines that are callable just like EFI runtime services), we are more likely to run into issues of this sort, and it is much more likely that we can identify and work around such issues if they don't bring down the system entirely. Since we already use a EFI runtime services call wrapper in assembler, we can quite easily add some code that captures the execution state at the point where the call is made, allowing us to revert to this state and proceed execution if the call triggered a synchronous exception. Given that the kernel and the firmware don't share any data structures that could end up in an indeterminate state, we can happily continue running, as long as we mark the EFI runtime services as unavailable from that point on. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2022-12-08Revert "ARM: dts: imx7: Fix NAND controller size-cells"Francesco Dolcini
This reverts commit 753395ea1e45c724150070b5785900b6a44bd5fb. It introduced a boot regression on colibri-imx7, and potentially any other i.MX7 boards with MTD partition list generated into the fdt by U-Boot. While the commit we are reverting here is not obviously wrong, it fixes only a dt binding checker warning that is non-functional, while it introduces a boot regression and there is no obvious fix ready. Fixes: 753395ea1e45 ("ARM: dts: imx7: Fix NAND controller size-cells") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Marek Vasut <marex@denx.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/Y4dgBTGNWpM6SQXI@francesco-nb.int.toradex.com/ Link: https://lore.kernel.org/all/20221205144917.6514168a@xps-13/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-08Merge tag 'asahi-soc-dt-6.2-v3' of https://github.com/AsahiLinux/linux into ↵Arnd Bergmann
soc/dt Apple SoC DT updates for 6.2 (v3). One final update for 6.2. This includes: * L1/L2 cache topology for t8103 * A bunch of typo, style, and minor functional fixes * tag 'asahi-soc-dt-6.2-v3' of https://github.com/AsahiLinux/linux: arm64: dts: apple: t6002: Fix GPU power domains arm64: dts: apple: t600x-pmgr: Fix search & replace typo arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes arm64: dts: apple: Rename dart-sio* to sio-dart* arch: arm64: apple: t600x: Use standard "iommu" node name arch: arm64: apple: t8103: Use standard "iommu" node name Link: https://lore.kernel.org/r/488ad4e9-04dc-1774-3bbe-d313ef30f14d@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-08Merge branch 'topic/objtool' into nextMichael Ellerman
Merge the powerpc objtool support, which we were keeping in a topic branch in case of any merge conflicts.
2022-12-08MIPS: OCTEON: cvmx-bootmem: use strscpy() to instead of strncpy()Xu Panda
The implementation of strscpy() is more robust and safer. Signed-off-by: Xu Panda <xu.panda@zte.com.cn> Signed-off-by: Yang Yang <yang.yang29@zte.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-12-08MIPS: mscc: jaguar2: Fix pca9545 i2c-mux node namesGeert Uytterhoeven
"make dtbs_check": arch/mips/boot/dts/mscc/jaguar2_pcb110.dtb: pca9545@70: $nodename:0: 'pca9545@70' does not match '^(i2c-?)?mux' From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml arch/mips/boot/dts/mscc/jaguar2_pcb110.dtb: pca9545@70: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c@0', 'i2c@1', 'i2c@2', 'i2c@3' were unexpected) From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml ... Fix this by renaming PCA9545 nodes to "i2c-mux", to match the I2C bus multiplexer/switch DT bindings and the Generic Names Recommendation in the Devicetree Specification. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-12-08USB: sisusbvga: remove console supportJiri Slaby (SUSE)
It was marked as BROKEN since commit 862ee699fefe (USB: sisusbvga: Make console support depend on BROKEN) 2 years ago. Since noone stepped up to fix it, remove it completely. Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: Thomas Winischhofer <thomas@winischhofer.net> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-sh@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Link: https://lore.kernel.org/r/20221208090749.28056-1-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-12-08arm64: efi: Execute runtime services from a dedicated stackArd Biesheuvel
With the introduction of PRMT in the ACPI subsystem, the EFI rts workqueue is no longer the only caller of efi_call_virt_pointer() in the kernel. This means the EFI runtime services lock is no longer sufficient to manage concurrent calls into firmware, but also that firmware calls may occur that are not marshalled via the workqueue mechanism, but originate directly from the caller context. For added robustness, and to ensure that the runtime services have 8 KiB of stack space available as per the EFI spec, introduce a spinlock protected EFI runtime stack of 8 KiB, where the spinlock also ensures serialization between the EFI rts workqueue (which itself serializes EFI runtime calls) and other callers of efi_call_virt_pointer(). While at it, use the stack pivot to avoid reloading the shadow call stack pointer from the ordinary stack, as doing so could produce a gadget to defeat it. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2022-12-08LoongArch: mm: Fix huge page entry update for virtual machineHuacai Chen
In virtual machine (guest mode), the tlbwr instruction can not write the last entry of MTLB, so we need to make it non-present by invtlb and then write it by tlbfill. This also simplify the whole logic. Signed-off-by: Rui Wang <wangrui@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-12-08LoongArch: Export symbol for function smp_send_reschedule()Bibo Mao
Function smp_send_reschedule() is standard kernel API, which is defined in header file include/linux/smp.h. However, on LoongArch it is defined as an inline function, this is confusing and kernel modules can not use this function. Now we define smp_send_reschedule() as a general function, and add a EXPORT_SYMBOL_GPL on this function, so that kernel modules can use it. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-12-08arm64: dts: apple: t6002: Fix GPU power domainsAsahi Lina
On t6002 (M1 Ultra), each die contains a self-contained GPU block. However, only the coprocessor and global management circuitry of the first die are used. This is what is represented by the "gpu" PS (the one in die1 is disabled). Nonetheless, this shared component drives the processing blocks in both dies, and therefore depends on the AFR fabric being powered up on both dies. Add an explicit dependency from the GPU block on die0 to AFR on die1, next to the existing die0 AFR dependency. Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Asahi Lina <lina@asahilina.net> Reviewed-by: Janne Grunau <j@jannau.net> Signed-off-by: Hector Martin <marcan@marcan.st>
2022-12-08arm64: dts: apple: t600x-pmgr: Fix search & replace typoAsahi Lina
It looks like the search-and-replace that happened to add die IDs to the t600x PMGR tree was a little bit too eager on a comment, and nobody noticed! Let's fix that. Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Asahi Lina <lina@asahilina.net> Reviewed-by: Janne Grunau <j@jannau.net> Signed-off-by: Hector Martin <marcan@marcan.st>
2022-12-08powerpc/prom: Fix 32-bit buildMichael Ellerman
Add an IS_ENABLED() check to fix the build error: arch/powerpc/kernel/prom.o: in function `early_init_dt_scan_cpus': prom.c:(.init.text+0x2ea): undefined reference to `boot_cpu_node_count' Fixes: e13d23a404f2 ("powerpc: export the CPU node count") Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2022-12-07Merge tag 'qcom-dts-for-6.2-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt More Qualcomm DTS updates for 6.2 This introduces support for the OnePlus One, on MSM8974Pro, and properly marks other Pro devices as compatible thereof. Also on MSM8974, the description of USB devices and their PHYs are cleaned up. On the binding side compatibles for recently added ARM and ARM64 boards are added. * tag 'qcom-dts-for-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (102 commits) dt-bindings: arm: qcom: Add zombie ARM: dts: qcom: msm8974: Add OnePlus One dt-bindings: arm: qcom: Document oneplus,bacon device ARM: dts: qcom: msm8974: clean up USB nodes arm: dts: qcom: use qcom,msm8974pro for pro devices dt-bindings: arm: qcom: split MSM8974 Pro and MSM8974 ARM: dts: qcom: align LED node names with dtschema dt-bindings: arm: qcom: Document additional sa8540p device dt-bindings: arm: qcom: Add Xperia 5 IV (PDX224) dt-bindings: arm: qcom: Document msm8956 and msm8976 SoC and devices dt-bindings: arm: add xiaomi,sagit board based on msm8998 chip dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible dt-bindings: arm: cpus: add qcom kryo 360 compatible ARM: dts: qcom-msm8960-cdp: align TLMM pin configuration with DT schema ARM: dts: qcom-msm8960: use define for interrupt constants dt-bindings: arm: qcom: Document SM6375 & Xperia 10 IV ARM: dts: qcom-apq8060: align TLMM pin configuration with DT schema ARM: dts: qcom: msm8226: Add MMCC node dt-bindings: arm: qcom: Separate LTE/WIFI SKU for sc7280-evoker dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards ... Link: https://lore.kernel.org/r/20221207153201.3233015-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-07Merge tag 'qcom-arm64-for-6.2-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt More Qualcomm ARM64 DT updates for 6.2 This introduce description of MSM8956 and MSM8976 and based on this adds Sony Xperia X and X Compact. It adds the SA8540P QDrive 3 automotive development board and enables PCIe on the same. Add description of the Vision Mezzanine for the RB5 board and the Navigation Mezzanine for the SDM845 RB3. SC8280XP adds L3 and DDR scaling support, resulting in good performance improvement. PCIe and UFS is marked DMA coherent, resolving data corruption issues. Reference clocks for UFS phy and device are corrected, to resolve issues seen in combinations with some bootloaders where it's not sufficient to rely on the bootloader state. RTC description is added to the SA8295P ADP board. For SM6115 GPI, PRNG, tsens, WCN, cpufreq, I2C/SPI and display blocks are added. On SM6375 QUP blocks are described, allowing the addition of touchscreen and remoteprocs for ADSP and CDSP are introduced. Sony Xperia 10 IV adds description of regulators, allowing enabling SD-card support. SM8250 Coresight components are described It introduces support for the Xiaomi Mi 6 on MSM8998 and adds flash LED to the Xiaomi Redmi 2. The SDHCI block on SM8350 is described and enabled on Sony Xperia 5 III. SM8450 sound and Soundwire blocks are described, and enabled on HDK. CPU supply clock is described, to satisfy the DT binding and the opp-framework. Sony Xperia 5 IV support is added, with touchscreen added. Lastly a range of changes to align DT source with their bindings. * tag 'qcom-arm64-for-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (98 commits) dt-bindings: iio: adc: qcom,spmi-vadc: fix PM8350 define dt-bindings: iio: adc: qcom,spmi-vadc: extend example arm64: dts: qcom: sc8280xp: fix UFS DMA coherency arm64: dts: qcom: sc7280: Add DT for sc7280-herobrine-zombie arm64: dts: qcom: sm8250-sony-xperia-edo: fix no-mmc property for SDHCI arm64: dts: qcom: sdm845-sony-xperia-tama: fix no-mmc property for SDHCI arm64: dts: qcom: sda660-inforce-ifc6560: fix no-mmc property for SDHCI arm64: dts: qcom: sa8155p-adp: fix no-mmc property for SDHCI arm64: dts: qcom: qrb5165-rb: fix no-mmc property for SDHCI arm64: dts: qcom: sm8450: align MMC node names with dtschema arm64: dts: qcom: sc7180-trogdor: use generic node names arm64: dts: qcom: sm8450-hdk: add sound support arm64: dts: qcom: sm8450: add Soundwire and LPASS arm64: dts: qcom: sm8450: add GPR node arm64: dts: qcom: sa8540p-ride: enable PCIe support arm64: dts: qcom: sm6115: Add smmu fallback to qcom generic compatible arm64: dts: qcom: sm6115: Add WCN node arm64: dts: qcom: sm6115: Add i2c/spi nodes arm64: dts: qcom: sm6115: Add GPI DMA arm64: dts: qcom: sm6115: Add mdss/dpu node ... Link: https://lore.kernel.org/r/20221207152554.3232434-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-07Merge tag 'socfpga_dts_updates_for_v6.2_part2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA dts updates for v6.2, part 2 - Fix dtschema for LED node - Fix dtschema for i2c-mux * tag 'socfpga_dts_updates_for_v6.2_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: Fix pca9548 i2c-mux node name ARM: dts: socfpga: align LED node names with dtschema arm64: dts: altera: align LED node names with dtschema Link: https://lore.kernel.org/r/20221206214006.590562-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-07arm64: efi: Limit allocations to 48-bit addressable physical regionArd Biesheuvel
The UEFI spec does not mention or reason about the configured size of the virtual address space at all, but it does mention that all memory should be identity mapped using a page size of 4 KiB. This means that a LPA2 capable system that has any system memory outside of the 48-bit addressable physical range and follows the spec to the letter may serve page allocation requests from regions of memory that the kernel cannot access unless it was built with LPA2 support and enables it at runtime. So let's ensure that all page allocations are limited to the 48-bit range. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2022-12-07Merge tag 'v6.1-rc8' into efi/nextArd Biesheuvel
Linux 6.1-rc8
2022-12-07Merge tag 'irqchip-6.2' of ↵Thomas Gleixner
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates frim Marc Zyngier: - More APCI fixes and improvements for the LoongArch architecture, adding support for the HTVEC irqchip, suspend-resume, and some PCI INTx workarounds - Initial DT support for LoongArch. I'm not even kidding. - Support for the MTK CIRQv2, a minor deviation from the original version - Error handling fixes for wpcm450, GIC... - BE detection for a FSL controller - Declare the Sifive PLIC as wake-up agnostic - Simplify fishing out the device data for the ST irqchip - Mark some data structures as __initconst in the apple-aic driver - Switch over from strtobool to kstrtobool - COMPILE_TEST fixes
2022-12-07ARM: 9279/1: support function error injectionWang Kefeng
This enables HAVE_FUNCTION_ERROR_INJECTION by adding necessary regs_set_return_value() and override_function_with_return(). Simply tested according to Documentation/fault-injection/fault-injection.rst. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-12-07ARM: 9278/1: kfence: only handle translation faultsWang Kefeng
This is a similar fixup like arm64 does, only handle translation faults in case of unexpected kfence report when alignment faults on ARM, see more from commit 0bb1fbffc631 ("arm64: mm: kfence: only handle translation faults"). Fixes: 75969686ec0d ("ARM: 9166/1: Support KFENCE for ARM") Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-12-07powerpc/rtas: mandate RTAS syscall filteringNathan Lynch
CONFIG_PPC_RTAS_FILTER has been optional but default-enabled since its introduction. It's been enabled in enterprise distro kernels for a while without causing ABI breakage that wasn't easily fixed, and it prevents harmful abuses of the rtas syscall. Let's make it unconditional. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-10-nathanl@linux.ibm.com
2022-12-07powerpc/rtas: define pr_fmt and convert printk call sitesNathan Lynch
Set pr_fmt to "rtas: " and convert the handful of printk() uses in rtas.c, adjusting the messages to remove now-redundant "RTAS" strings. Note that rtas_restart(), rtas_power_off(), and rtas_halt() all currently use printk() without specifying a log level. These have been changed to use pr_emerg(), which matches the behavior of rtas_os_term(). Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-9-nathanl@linux.ibm.com
2022-12-07powerpc/rtas: clean up includesNathan Lynch
rtas.c used to host complex code related to pseries-specific guest migration and suspend, which used atomics, completions, hcalls, and CPU hotplug APIs. That's all been deleted or moved, so remove the include directives that have been rendered unnecessary. Sort the remainder (with linux/ before asm/) to impose some order on where future additions go. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-8-nathanl@linux.ibm.com
2022-12-07powerpc/rtas: clean up rtas_error_log_max initializationNathan Lynch
The code in rtas_get_error_log_max() doesn't cause problems in practice, but there are no measures to ensure that the lazy initialization of the static rtas_error_log_max variable is atomic, and it's not worth adding them. Initialize the static rtas_error_log_max variable at boot when we're single-threaded instead of lazily on first use. Use the more appropriate of_property_read_u32() API instead of rtas_token() to consult the "rtas-error-log-max" property, which is not the name of an RTAS function. Convert use of printk() to pr_warn() and distinguish the possible error cases. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-7-nathanl@linux.ibm.com
2022-12-07powerpc/pseries/eeh: use correct API for error log sizeNathan Lynch
rtas-error-log-max is not the name of an RTAS function, so rtas_token() is not the appropriate API for retrieving its value. We already have rtas_get_error_log_max() which returns a sensible value if the property is absent for any reason, so use that instead. Fixes: 8d633291b4fc ("powerpc/eeh: pseries platform EEH error log retrieval") Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> [mpe: Drop no-longer possible error handling as noticed by ajd] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-6-nathanl@linux.ibm.com
2022-12-07powerpc/rtas: avoid scheduling in rtas_os_term()Nathan Lynch
It's unsafe to use rtas_busy_delay() to handle a busy status from the ibm,os-term RTAS function in rtas_os_term(): Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b BUG: sleeping function called from invalid context at arch/powerpc/kernel/rtas.c:618 in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 1, name: swapper/0 preempt_count: 2, expected: 0 CPU: 7 PID: 1 Comm: swapper/0 Tainted: G D 6.0.0-rc5-02182-gf8553a572277-dirty #9 Call Trace: [c000000007b8f000] [c000000001337110] dump_stack_lvl+0xb4/0x110 (unreliable) [c000000007b8f040] [c0000000002440e4] __might_resched+0x394/0x3c0 [c000000007b8f0e0] [c00000000004f680] rtas_busy_delay+0x120/0x1b0 [c000000007b8f100] [c000000000052d04] rtas_os_term+0xb8/0xf4 [c000000007b8f180] [c0000000001150fc] pseries_panic+0x50/0x68 [c000000007b8f1f0] [c000000000036354] ppc_panic_platform_handler+0x34/0x50 [c000000007b8f210] [c0000000002303c4] notifier_call_chain+0xd4/0x1c0 [c000000007b8f2b0] [c0000000002306cc] atomic_notifier_call_chain+0xac/0x1c0 [c000000007b8f2f0] [c0000000001d62b8] panic+0x228/0x4d0 [c000000007b8f390] [c0000000001e573c] do_exit+0x140c/0x1420 [c000000007b8f480] [c0000000001e586c] make_task_dead+0xdc/0x200 Use rtas_busy_delay_time() instead, which signals without side effects whether to attempt the ibm,os-term RTAS call again. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-5-nathanl@linux.ibm.com
2022-12-07powerpc/rtas: avoid device tree lookups in rtas_os_term()Nathan Lynch
rtas_os_term() is called during panic. Its behavior depends on a couple of conditions in the /rtas node of the device tree, the traversal of which entails locking and local IRQ state changes. If the kernel panics while devtree_lock is held, rtas_os_term() as currently written could hang. Instead of discovering the relevant characteristics at panic time, cache them in file-static variables at boot. Note the lookup for "ibm,extended-os-term" is converted to of_property_read_bool() since it is a boolean property, not an RTAS function token. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> [mpe: Incorporate suggested change from Nick] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-4-nathanl@linux.ibm.com
2022-12-07powerpc/rtasd: use correct OF API for event scan rateNathan Lynch
rtas_token() should be used only for properties that are RTAS function tokens. "rtas-event-scan-rate" does not contain a function token, but it has the same size/format as token properties so reading it with rtas_token() happens to work. Convert to of_property_read_u32(). Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-3-nathanl@linux.ibm.com
2022-12-07powerpc/rtas: document rtas_call()Nathan Lynch
rtas_call() has a complex calling convention, non-standard return values, and many users. Add kernel-doc for it and remove the less structured commentary from rtas.h. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221118150751.469393-2-nathanl@linux.ibm.com
2022-12-07powerpc/pseries: unregister VPA when hot unplugging a CPULaurent Dufour
The VPA should unregister when offlining a CPU. Otherwise there could be a short window where 2 CPUs could share the same VPA. This happens because the hypervisor is still keeping the VPA attached to the vCPU even if it became offline. Here is a potential situation: 1. remove proc A, 2. add proc B. If proc B gets proc A's place in cpu_present_mask, then it registers proc A's VPAs. 3. If proc B is then re-added to the LP, its threads are sharing VPAs with proc A briefly as they come online. As the hypervisor may check for the VPA's yield_count field oddity, it may detect an unexpected value and kill the LPAR. Suggested-by: Nathan Lynch <nathanl@linux.ibm.com> Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> Reviewed-by: Nathan Lynch <nathanl@linux.ibm.com> [mpe: s/cpu_present_map/cpu_present_mask/ in change log] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221114160150.13554-1-ldufour@linux.ibm.com
2022-12-07powerpc/pseries: reset the RCU watchdogs after a LPMLaurent Dufour
The RCU watchdog timer should be reset when restarting the CPU after a Live Partition Mobility operation. Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> Acked-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Combine comments into a single comment block] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221125173204.15329-1-ldufour@linux.ibm.com
2022-12-07powerpc: Take in account addition CPU node when building kexec FDTLaurent Dufour
On a system with a large number of CPUs, the creation of the FDT for a kexec kernel may fail because the allocated FDT is not large enough. When this happens, such a message is displayed on the console: Unable to add ibm,processor-vadd-size property: FDT_ERR_NOSPACE The property's name may change depending when the buffer overwrite is detected. Obviously the created FDT is missing information, and it is expected that system dump or kexec kernel failed to run properly. When the FDT is allocated, the size of the FDT the kernel received at boot time is used and an extra size can be applied. Currently, only memory added after boot time is taken in account, not the CPU nodes. The extra size should take in account these additional CPU nodes and compute the required extra space. To achieve that, the size of a CPU node, including its subnode is computed once and multiplied by the number of additional CPU nodes. The assumption is that the size of the CPU node is _same_ for all the node, the only variable part should be the name "PowerPC,POWERxx@##" where "##" may vary a little. Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> [mpe: Don't shadow function name w/variable, minor coding style changes] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221110180619.15796-3-ldufour@linux.ibm.com
2022-12-07powerpc: export the CPU node countLaurent Dufour
At boot time, the FDT is parsed to compute the number of CPUs. In addition count the number of CPU nodes and export it. This is useful when building the FDT for a kexeced kernel since we need to take in account the CPU node added since the boot time during CPU hotplug operations. Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221110180619.15796-2-ldufour@linux.ibm.com
2022-12-07RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpidAnup Patel
We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid so that KVM user-space can change this details to support migration across heterogeneous hosts. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPUAnup Patel
We should save VCPU mvendorid, marchid, and mimpid at the time of creating VCPU so that we don't have to do host SBI call every time Guest/VM ask for these details. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: Export sbi_get_mvendorid() and friendsAnup Patel
The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid() can be used by KVM module so let us export these functions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.hAnup Patel
Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct and functions in asm/kvm_vcpu_sbi.h. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()Anup Patel
We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions because the else-if ladder is quite big now. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Remove redundant includes of asm/csr.hAnup Patel
We should include asm/csr.h only where required so let us remove redundant includes of this header. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.hAnup Patel
The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c so let us remove it. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()Anup Patel
The reg_val check in kvm_riscv_vcpu_set_reg_config() should only be done for isa config register. Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Simplify kvm_arch_prepare_memory_region()Christophe JAILLET
In kvm_arch_prepare_memory_region(), if no error occurs, a spin_lock()/ spin_unlock() call can be avoided. Switch to kvm_riscv_gstage_iounmap() that is the same as the current code, but with a better semantic. It also embeds the locking logic. So it is avoided if ret == 0. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Exit run-loop immediately if xfer_to_guest failsAnup Patel
If xfer_to_guest_mode_handle_work() fails in the run-loop then exit the run-loop immediately instead of doing it after some more work. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: use vma_lookup() instead of find_vma_intersection()Bo Liu
vma_lookup() finds the vma of a specific address with a cleaner interface and is more readable. Signed-off-by: Bo Liu <liubo03@inspur.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07RISC-V: KVM: Add exit logic to main.cXiakaiPan
Several lines of code are inserted to remove KVM module normally using rmmod command just like others. Signed-off-by: XiakaiPan <13212017962@163.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-12-07arm64: dts: apple: Add t8103 L1/L2 cache properties and nodesJanne Grunau
The t8103 CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions. The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described. Based on Rob Herring's patch adding cache properties and nodes for t600x. Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/ Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Hector Martin <marcan@marcan.st>