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2023-06-20Merge tag 'ti-k3-dt-for-v6.5' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.5 New Boards: phyBOARD-Lyra-AM625 Board support Toradex Verdin AM62 COM, carrier and dev boards New features: Across K3 SoCs: - Error Signaling Module(ESM) and Secproxy IPC modules - On board I2C EEPROM - Voltage Temp Monitoring (VTM) module - DM timers (GP Timers) J784s4: - R5 and C7x DSP remoteproc, ADC, QSPI AM69: - Addition of more peripherals: CPSW, eMMC, UARTs, I2C et al J721s2: - USB, Serdes, OSPI, PCIe AM62a: - Watchdog J721e: - HyperFlash/HyperBus AM62: - Type-C USB0 port Cleanups and non-urgent fixes Particularly large set of cleanups to get rid of dtbs_check errors and dtc warnings: - Addition of missing pinmux and uart nodes for AM64, AM62x, AM62A, J721e, J7200 that are used by bootloader - Split Pinmux regions/range to avoid holes for J721s2, J7200, J784s4 - Drop bootargs and unneeded aliases across all K3 SoCs - Move aliases to board dts files from SoC dtsi files - Move to generic node name for can, rtc nodes on am65 - s/-pins-default/default-pins/ to match upcoming pinctrl.yaml update - Fix pinctrl phandle references to use <> as separator where multiple entries are present * tag 'ti-k3-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (153 commits) arm64: dts: ti: Unify pin group node names for make dtbs checks arm64: dts: ti: add verdin am62 yavia arm64: dts: ti: add verdin am62 dahlia arm64: dts: ti: add verdin am62 dt-bindings: arm: ti: add toradex,verdin-am62 et al. arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware arm64: dts: ti: k3-j7200-mcu-wakeup: Remove 0x unit address prefix from nodename arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom arm64: dts: ti: k3-am64: Add ESM support arm64: dts: ti: k3-am62: Add ESM support arm64: dts: ti: k3-j7200: Add ESM support arm64: dts: ti: k3-j721e: Add ESM support dt-bindings: misc: esm: Add ESM support for TI K3 devices arm64: dts: ti: k3-j721s2-som-p0: Enable wakeup_i2c0 and eeprom arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux arm64: dts: ti: k3-am68-sk-som: Enable wakeup_i2c0 and eeprom arm64: dts: ti: k3-am68-sk-base-board: Add uart pinmux arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi Header arm64: dts: ti: k3-j721s2: Fix wkup pinmux range ... Link: https://lore.kernel.org/r/7fe0c6de-cb99-9c89-8583-b3855fde16f8@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'zynqmp-dt-for-v6.5' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann
soc/dt arm64: ZynqMP DT changes for v6.5 Various small fixes and cleanups to be aligned with the latest dt-schema. Other major changes are: - Wire mali-400 gpu - Change board name for zcu1275 - Use ethernet-phy-id to handle ETH phy reset properly - Switch to amd.com emails - Update people in DT bindings * tag 'zynqmp-dt-for-v6.5' of https://github.com/Xilinx/linux-xlnx: (33 commits) dt-bindings: usb: xilinx: Replace Manish by Piyush dt-bindings: xilinx: Remove Rajan, Jolly and Manish arm64: zynqmp: Used fixed-partitions for QSPI in k26 arm64: zynqmp: Add pmu interrupt-affinity arm64: zynqmp: Set qspi tx-buswidth to 4 arm64: zynqmp: Fix usb node drive strength and slew rate arm64: zynqmp: Describe TI phy as ethernet-phy-id arm64: zynqmp: Switch to amd.com emails arm64: zynqmp: Convert kv260-revA overlay to ASCII text dt-bindings: xilinx: Switch xilinx.com emails to amd.com arm64: xilinx: Use zynqmp prefix for SOM dt overlays arm64: zynqmp: Add phase tags marking arm64: zynqmp: Describe bus-width for SD card on KV260 arm64: zynqmp: Enable AMS on SOM and other zcu10x boards arm64: zynqmp: Enable DP driver for SOMs arm64: zynqmp: Setup clock for DP and DPDMA arm64: zynqmp: Switch to ethernet-phy-id in kv260 arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2 arm64: zynqmp: Add pinctrl emmc description to SM-K26 arm64: zynqmp: Add gpio labels for modepin gpio ... Link: https://lore.kernel.org/r/CAHTX3d+2s_KmCnd=x5hydGb+LYoznAzYGTizvqqN2NFmrBurfw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'riscv-dt-for-v6.5' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.5 StarFive: Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P being power, support for the JH7110. PMIC and frequency scaling support for the JH7110 equipped VisionFive 2. Most of the DT bits for the JH7110, and the SBCs using it, are pending support for one of the clock controllers, so it's a smaller set of changes than I would have hoped for. Misc: Pick up some dt-binding cleanup that Palmer assigned to me & had no uptake from the respective maintainers. My powers of estimation failed me again, with part of my motivation for picking them up being the addition of new platforms that ended up not making it. Hopefully next window for those, as they were relatively close. Exclude the Allwinner and Renesas subdirectories from the Misc. MAINTAINERS entry, since I do not take care of those. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: Add cpu scaling for JH7110 SoC riscv: dts: starfive: Enable axp15060 pmic for cpufreq dt-bindings: interrupt-controller: sifive,plic: Sort compatible values dt-bindings: timer: sifive,clint: Clean up compatible value section riscv: dts: starfive: jh7110: Add watchdog node riscv: dts: starfive: jh7100: Add watchdog node riscv: dts: starfive: Add PMU controller node MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry Link: https://lore.kernel.org/r/20230612-fasting-floss-0bc05a08bc7a@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controllerSam Protsenko
As described in the corresponding binding documentation for "samsung,exynos850-pmu", the "clocks" property should be used for specifying CLKOUT mux inputs. Therefore, the clock provided to exynos850 pmu_system_controller is incorrect and should be removed. Instead of making syscon regmap keep that clock running for PMU accesses, it should be made always running in the clock driver, because the kernel is not the only software accessing PMU registers on Exynos850 platform. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230308233822.31180-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230612180102.289745-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'v6.5-rockchip-dts64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards are - Indiedroid Nova (rk3588) - Add Edgeble Neural Compute Module 6B (rk3588) - FriendlyARM NanoPi R2C Plus (rk3328) - Anbernic RG353PS (rk3566) - Lunzn Fastrhino R66S / R68S (rk3568) The rk3588 got a lot of attention and gained support for the GIC ITS (needed an errata from Rockchip), timers, otp memory, saradc and sdio. The rk356x got support for its RGA block With all the core improvements to rk3588 support, the Rock5b got a lot improvements from that too, namely support for its PMIC, sd-card and saradc, as well as a clock-rate fix for its es8316 codec. Similarly the rk3588-evb1 also got support for its PMIC. The Anberic RGxx3 series got a better bluetooth compatible and updates to its LEDs to make them use the PWM blocks they're connected to. * tag 'v6.5-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (29 commits) arm64: dts: rockchip: Add saradc node to rock5b arm64: dts: rockchip: Fix compatible for Bluetooth on rk3566-anbernic arm64: dts: rockchip: Add SD card support to rock-5b arm64: dts: rockchip: add PMIC to rock-5b arm64: dts: rockchip: Assign ES8316 MCLK rate on rk3588-rock-5b arm64: dts: rockchip: Add Indiedroid Nova board dt-bindings: arm: rockchip: Add Indiedroid Nova dt-bindings: vendor-prefixes: add Indiedroid arm64: dts: rockchip: Add sdio node to rk3588 arm64: dts: rockchip: add default pinctrl for rk3588 emmc arm64: dts: rockchip: Add DT node for ADC support in RK3588 arm64: dts: rockchip: add PMIC to rk3588-evb1 arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B IO arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B SoM arm64: dts: rockchip: Add Rockchip RK3588J dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 6B arm64: dts: rockchip: Add RGA2 support to rk356x media: dt-bindings: media: rockchip-rga: add rockchip,rk3568-rga arm64: dts: rockchip: Add rk3588 OTP node arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus ... Link: https://lore.kernel.org/r/3239799.44csPzL39Z@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'qcom-dts-for-6.5' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm ARM32 DeviceTree updates for v6.5 NAND support on IPQ4019 boards is restored, after a faulty node rename. On MSM8226 IMEM, PMU and RPM stats are introduced. The Huawei Watch gains vibrator support. On MSM8974, the LGE Nexus 5 gains vibrator support. The APQ8074 Dragonboard marks BLSP2 BAM controlled remotely, DSI panel, audio and modem DSPs are enabled. On SDX65 PCIe controller and PHY are introduced, to provide endpoint functionality. This is enabled on the related MTP. A range of DeviceTree cleanups are also included. * tag 'qcom-dts-for-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) ARM: dts: qcom: apq8074-dragonboard: enable DSI panel ARM: dts: qcom: apq8074-dragonboard: enable adsp and MSS ARM: dts: qcom: apq8074-dragonboard: Set DMA as remotely controlled ARM: dts: qcom: apq8026-huawei-sturgeon: Add vibrator ARM: dts: qcom: msm8226: Add IMEM node ARM: dts: qcom: msm8226: Add rpm-stats device node ARM: dts: qcom: msm8226: Add PMU node ARM: dts: qcom: sdx65-mtp: Enable PCIe EP ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY ARM: dts: qcom: sdx65: Add support for PCIe EP ARM: dts: qcom: sdx65: Add support for PCIe PHY ARM: dts: qcom: msm8974: align WCNSS Bluetooth node name with bindings ARM: dts: qcom: apq8084: correct thermal sensor unit-address ARM: dts: qcom: msm8960-cdp: move regulator out of simple-bus ARM: dts: qcom: apq8060-dragonboard: move regulators out of simple-bus ARM: dts: qcom: ipq8064: align USB node names with bindings ARM: dts: qcom: ipq8064: correct LED node names ARM: dts: qcom: ipq8064: drop invalid GCC thermal-sensor unit-address ARM: dts: qcom: ipq8064: drop leading 0 from unit-address ARM: dts: qcom: msm8974: correct pronto unit-address ... Link: https://lore.kernel.org/r/20230611010843.2482142-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'qcom-arm64-for-6.5' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm ARM64 DeviceTree updates for v6.5 This introduces the RDP442 and RDP433 reference devices on IPQ5332 and IPQ9574, respectively. RDP418, RDP433, RDP449 and RDP453 on the IPQ9574 are added. On MSM8939 the Square T2 board and the Sony Xperia M4 Aqua is added. Support for Acer Apire 1, built on the Snapdragon 7c platform is introduced. Fxtec Pro1X on SM6115 is added. Lastly long floating support for SC8180X and the Lenovo Flex 5G, and the Primus reference device, has been added. On IPQ5332 and IPQ6018 QFPROM support is introduced, and as described above the RDP442 board on the prior. Download mode support and various reserved-memory regions are also introduced on IPQ6018. IPQ8074 gains another SPI controller. On IPQ9574 CPU frequency scaling, low speed busses, RNG, Watchdog, qfprom, SMEM and RPM are introduced. As are support for four new board, mentioned above. MSM8916 gains a range of structural improvements, to better suite the various boards supported. Regulator constraints are corrected and their states are adjusted to match reality (e.g. always-on regulators marked as always-on). BQ Aquaris X5 gains support for front flash LED. As mentioned above, MSM8939 support is introduced with support for boards from Sony and Square. MSM8953 gains DMA support in I2C masters. MSM8996-based Sony Xperia boards gains description of their RGB notification LED. On SA8775P support for UFS, USB, GPU clock and iommu controllers, PMU, AOSS, watchdog and missing low-speed controllers are added. On the Ride platform UFS, USB and an i2c bus are enabled. iommu properties are added to QSPI on both SC7180 and SC7280. LPASS clocks are adjusted and MDP node cleaned up slightly, on SC7180. As mentioned above, support for Acer Aspire 1 is introduced. Long lingering patches introducing SC8180X, the Lenovo Flex 5G and the Primus reference device has been merged. On SC8280XP ethernet is added and enabled on the automotive ride platform. An SDC controller is introduced and enabled on the SC8280XP CRD. On the Lenovo Thinkpad X13s and the CRD reference device the USB SuperSpeed phy is added to the Type-C graph, to enable support for orientation switching. Fairphone 3 gains support for its notification LED. On SDM845 the iommu stream for QSPI is defined, SHIFT SHIFT6mq gains support for flash LED and the RB3 (DB845c) board gains support for bonded/dual DSI-mode, to allow 4k output. On SM6115 CPU idle-states, crypto engine support and SuperSpeed USB PHY are introduced. As mentioned above Fxtec Pro1X is introduced. On the QRB4210 Robotics Platform RB2 USB, Audio and Compute DSPs, display, CAN-bus and GPIO LEDs are introduced, fixed regulators are described and the SD-card description is corrected. Support for crypto engine is added to SM8150, while Sony Xperia 1 and 5 gains SD-card support, camera regulators and GPIO line names sorted out. SM8250 also gets support for crypto engine, and Sony Xperia 1 II and 5 II gains support for hardware video accelerator. Crypto engine is introduced for SM8350 as well. The HDK gets the USB Type-C graph described for Superspeed orientation switching and DisplayPort output. On SM8450 video clock controller and crypto engine are added, missing opp levels are introduced and the USB Type-C graph is defined for orientation switching and altmode. SM8550 gains GPU and video clock controllers and missing opp levels are added. The WCD9385 audio codec is added for the SM8550 MTP and on the QRD PCIe, USB, audio display and flash LED are added. * tag 'qcom-arm64-for-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (195 commits) arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G arm64: dts: qcom: sc8180x: Introduce Primus arm64: dts: qcom: sc8180x: Add pmics arm64: dts: qcom: sc8180x: Add display and gpu nodes arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes arm64: dts: qcom: sc8180x: Add PCIe instances arm64: dts: qcom: sc8180x: Add QUPs arm64: dts: qcom: sc8180x: Add thermal zones arm64: dts: qcom: sc8180x: Add interconnects and lmh arm64: dts: qcom: Introduce the SC8180x platform arm64: dts: qcom: msm8916: Move aliases to boards arm64: dts: qcom: pm8916: Rename &wcd_codec -> &pm8916_codec arm64: dts: qcom: msm8916/39: Clean up MDSS labels arm64: dts: qcom: msm8916/39: Use consistent name for I2C/SPI pinctrl arm64: dts: qcom: msm8916/39: Rename &blsp1_uartN -> &blsp_uartN arm64: dts: qcom: msm8916: Rename &msmgpio -> &tlmm arm64: dts: qcom: qrb4210-rb2: Enable USB node arm64: dts: qcom: sm6115: Add USB SS qmp phy node arm64: dts: qcom: ipq5332: add support for the RDP442 variant dt-bindings: arm: qcom: document MI01.3 board based on IPQ5332 family ... Link: https://lore.kernel.org/r/20230611004944.2481596-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'imx-dt64-6.5' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX arm64 device tree for 6.5: - New board support: i.MX8MM based Emtop SoM & Baseboard, NXP i.MX8MM EVKB board, i.MX8MP based Gateworks Venice gw7905-2x device. - A series from Adam Ford to add Camera and Audio support for i.MX8M based Beacon boards. - Add Audio output support for i.MX8MP TQMa8MPxL/MBa8MPxL board. - Add HDMI and display support for imx8mm-evk and imx8mm-phg board. - Add coresight trace devices support for i.MX8MP SoC. - A couple of changes from Krzysztof Kozlowski to add missing cache properties. - A couple of changes from Laurent Pinchart to add CSIS and ISI devices for i.MX8MP SoC. - A series from Marek Vasut to add more devices for i.MX8MP, and enable SAI audio on i.MX8MP DHCOM PDK2 and PDK3. - Correct GSC vdd_bat data size for Gateworks Venice devices. - Add more device support for i.MX93, Watchdog, OCOTP, idle states, DDR performance monitor, etc. - Small and random clean-ups and device node additions. * tag 'imx-dt64-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (47 commits) arm64: dts: imx8mq: Pass address-cells/size-cells to mipi_dsi arm64: dts: imx8mq: Use 'dsi' as node name arm64: dts: imx8mp-venice-gw702x: fix GSC vdd_bat data size arm64: dts: imx8mq-tqma8mq-mba8mx: Remove invalid properties arm64: dts: imx8mq: Add missing pci property arm64: dts: imx8mq: Fix lcdif clocks arm64: dts: imx8mq: Fix lcdif compatible arm64: dts: imx8mp: don't initialize audio clocks from CCM node arm64: dts: imx8mm-venice: Fix GSC vdd_bat data size. arm64: dts: imx8mp: Add coresight trace components arm64: dts: imx93: add ddr performance monitor node arm64: dts: imx8mm-phg: Add display support arm64: dts: tqma8mqml: Add vcc supply to i2c eeproms arm64: dts: imx8mm-evk: Add HDMI support arm64: dts: imx8mn-var-som-symphony: adapt FEC pinctrl for SOMs with onboard PHY arm64: dts: imx8mn-var-som: add 20ms delay to ethernet regulator enable arm64: dts: imx8mp-msc-sm2s: Add sound card arm64: dts: imx8mn-beacon: Migrate sound card to simple-audio-card arm64: dts: imx8mp-beacon-kit: Enable WM8962 Audio CODEC arm64: dts: imx93: add fsl,stop-mode property to support WOL ... Link: https://lore.kernel.org/r/20230610072530.418847-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'imx-dt-6.5' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX ARM device tree for 6.5: - New board support: Marantec Maveo Box. - Add HDMI support for TQMa6x/MBa6 board. - A series from Andrew Lunn to add phy-mode and fixed links for Ethernet devices on imx51, imx6qdl and vf610. - A bunch of changes from Fabio Estevam to clean up deprecated and invalid properies, fix up node names to remove dt-schema warnings. - A series of maintenance updates for Protonic Holland boards, mostly on the USB subsystem configuration, thermal zones, and the naming of GPIO keys. - Update dma-apbh device node name to remove dtbs_check warnings. - Remove invalid nodes from fan-controller for a couple of Gateworks boards. - Small random updates and clean-ups on various boards. * tag 'imx-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (53 commits) ARM: dts: imx6qdl: vicut1: rename power to power-button ARM: dts: imx6dl: prtrvt, prtvt7, prti6q, prtwd2: fix USB related warnings ARM: dts: imx6dl: plybas: fix USB over-current detection on USB OTG port ARM: dts: imx6ul: prti6g: fix USB over-current detection on USB OTG port ARM: dts: imx6qp: prtwd3: Enable USB over current detection on USB OTG port ARM: dts: imx6dl: prtmvt: fix different USB related warnings ARM: dts: imx6dl: alti6p: fix different USB related warnings ARM: dts: imx6dl: vicut1: Address USB related warnings ARM: dts: imx6dl: Add trip points to thermal zones on several devices ARM: dts: imx6dl: lanmcu: Configure over-current polarity for USB OTG node ARM: dts: imx6dl: lanmcu: Disable unused USB PHY nodes ARM: dts: imx6q: prtwd2: Correct iomux configuration for ENET MDIO and MDC ARM: dts: imx6dl: prtvt7: Remove touchscreen inversion ARM: dts: imx6dl: prtvt7: Adjust default backlight brightness to 65 ARM: dts: imx6qdl: vicut1: The sgtl5000 uses i2s not ac97 ARM: dts: imx: Use 'eeprom' as node name ARM: dts: imx6ul-ccimx6ulsom: Fix the "coin" regulator name ARM: dts: imx: Use 'pmic' as node name ARM: dts: imx6: Use the mux- prefix ARM: dts: imx7d-sdb: Allow UHS modes ... Link: https://lore.kernel.org/r/20230610072530.418847-2-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'sunxi-dt-for-6.5-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - fix DCLK clock names - new board ICnova A20 ADB4006 - add D1 SPI node - add bluetooth node for chip board - add extra mmc2 pinmux to sun5i - add axp209 iio-hwmon node * tag 'sunxi-dt-for-6.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: axp209: Add iio-hwmon node for internal temperature ARM: dts: sun5i: Add port E pinmux settings for mmc2 ARM: dts: sun5i: chip: Enable bluetooth riscv: dts: allwinner: d1: Add SPI controllers node arm: dts: sunxi: Add ICnova A20 ADB4006 board dt-bindings: arm: sunxi: add ICnova A20 ADB4006 binding ARM: dts: sunxi: rename tcon's clock output Link: https://lore.kernel.org/r/20230609210452.GA17638@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20uml: Replace strlcpy with strscpyAzeem Shaikh
strlcpy() reads the entire source buffer first. This read may exceed the destination size limit. This is both inefficient and can lead to linear read overflows if a source string is not NUL-terminated [1]. In an effort to remove strlcpy() completely [2], replace strlcpy() here with strscpy(). No return values were used, so direct replacement is safe. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html#strlcpy [2] https://github.com/KSPP/linux/issues/89 Signed-off-by: Azeem Shaikh <azeemshaikh38@gmail.com> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20230614003604.1021205-1-azeemshaikh38@gmail.com
2023-06-20Merge tag 'tegra-for-6.5-arm64-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.5-rc1 This introduces support for the IGX Orin and Jetson Orin Nano devices and enables various additional features on the Jetson AGX Orin and Jetson Orin NX. This also enables some basic thermal support to prevent the devices from overheating. Support for the GPU on the Google Pixel C is enabled and various minor issues are fixed and cleaned up. * tag 'tegra-for-6.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Enable thermal support on Jetson Orin Nano arm64: tegra: Enable thermal support on Jetson Orin NX arm64: tegra: Enable thermal support on Jetson AGX Orin arm64: tegra: Add Tegra234 thermal support arm64: tegra: Add a few blank lines for better readability arm64: tegra: Sort properties more logically arm64: tegra: Enable GPU on Smaug arm64: tegra: Add GPU power rail regulator on Smaug arm64: tegra: Update USB phy-name for Jetson Orin NX arm64: tegra: Enable USB device for Jetson AGX Orin arm64: tegra: Add Tegra234 pin controllers arm64: tegra: Support Jetson Orin Nano Developer Kit arm64: tegra: Add missing cache properties on Tegra210 arm64: tegra: Fix PCIe regulator for Orin Jetson AGX arm64: tegra: Add CPU OPP tables and interconnects property arm64: tegra: Add support for IGX Orin Link: https://lore.kernel.org/r/20230609193620.2275240-6-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'stm32-dt-for-v6.5-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.5, round 1 Highlights: ---------- - MCU/MPU: - Replace deprecated st,hw-flow-ctrl by uart-has-rtscts. - Fix LTDC/DSI warnings. - MPU: - STMP32MP15: - Add OTP part number and Vrefint calibration in bsec. - M4 hold management updated. As SMC call is deprecated, the service is moved on a SCMI service. - Add ADC internal channels (VREFINT/VDDCORE). - ST: - Enable ADC1&2 on STM32MP15 DKx boards. - Adopt generic IIO bindings on STM32MP157C ED1 - Add supplies for OV5640 in STM32MP157C EV1 to fix yaml validation. - Fix i2s bindings to match with the YAML validation (DKx boards). - DH: - Rearrange MAC EEPROM. - Rename AV96 sound card. - Adopt generic IIo bindings. - Fix audio routing. -PHYTEC: - Add PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM. This SOM embeds up to 1GB DDR3LP RAM, up to 1GB eMMC, up to 16 MB QSPI and up to 128 GB NAND flash. * tag 'stm32-dt-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (34 commits) ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2 ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1 ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1 ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards ARM: dts: stm32: add vrefint support to adc2 on stm32mp15 ARM: dts: stm32: add vrefint calibration on stm32mp15 ARM: dts: stm32: add adc internal channels to stm32mp15 ARM: dts: stm32: fix ltdc warnings in stm32mp15 boards ARM: dts: stm32: fix dsi warnings on stm32mp15 boards dt-bindings: display: st,stm32-dsi: Remove unnecessary fields ARM: dts: stm32: fix warnings on stm32f469-disco board ARM: dts: stm32: Shorten the AV96 HDMI sound card name ARM: dts: stm32: fix m4_rproc references to use SCMI for stm32mp15 ARM: dts: stm32: Update Cortex-M4 reset declarations on stm32mp15 ARM: dts: stm32: add STM32MP1-based Phytec board ... Link: https://lore.kernel.org/r/08d711de-bb6d-a976-735b-5e18b19818ea@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'stm32-mp25-for-v6.5-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/newsoc STM32 STM32MP25 for v6.5, round 1 Highlights: ---------- STM32MP25 family is composed of 4 SoCs defined as following: -STM32MP251: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ... -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and LVDS display. -STM32MP255: STM32MP253 + GPU/AI and video encode/decode. -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports). A second diversity layer exists for security features/A35 frequency: -STM32MP25xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. This PR adds the STM32MP257F EV1 board support. This board embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... * tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (44 commits) MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE arm64: defconfig: enable ARCH_STM32 and STM32 serial driver arm64: dts: st: add stm32mp257f-ev1 board support dt-bindings: stm32: document stm32mp257f-ev1 board arm64: dts: st: introduce stm32mp25 pinctrl files arm64: dts: st: introduce stm32mp25 SoCs family arm64: introduce STM32 family on Armv8 architecture dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon pinctrl: stm32: add stm32mp257 pinctrl support dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2 ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1 ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1 ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards ARM: dts: stm32: add vrefint support to adc2 on stm32mp15 ... Link: https://lore.kernel.org/r/080fc303-45c1-6cc0-4c5e-694e730896a6@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20s390/cpum_cf: open access to hwctr device for CAP_PERFMON privileged processThomas Richter
The device /dev/hwctr was introduced to access complete CPU Measurement facility counter sets via an ioctl system call. The access the to device is limited to privileged processes running as root or superuser. The capability CAP_SYS_ADMIN is required. The device permissions are read/write for the device owner root. There is no need for this restriction. Make the device access permission read/write for all and reduce the capabilities to CAP_PERFMON. Any user space program with the CAP_PERFMON capability assigned to it can now read and display the CPU Measurement facility counter sets. For more details on perf tool usage and security, see linux documentation in Documentation/admin-guide/perf-security.rst. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2023-06-20s390/module: fix rela calculation for R_390_GOTENTSumanth Korikkar
During module load, module layout allocation occurs by initially allowing the architecture to frob the sections. This is performed via module_frob_arch_sections(). However, the size of each module memory types like text,data,rodata etc are updated correctly only after layout_sections(). After calculation of required module memory sizes for each types, move_module() is responsible for allocating the module memory for each type from modules vaddr range. Considering the sequence above, module_frob_arch_sections() updates the module mod_arch_specific got_offset before module memory text type size is fully updated in layout_sections(). Hence mod_arch_specific got_offset points to currently zero. As per s390 ABI, R_390_GOTENT : (G + O + A - P) >> 1 where G=me->mem[MOD_TEXT].base+me->arch.got_offset O=info->got_offset A=rela->r_addend P=loc fix R_390_GOTENT calculation in apply_rela(). Note: currently this doesn't break anything because me->arch.got_offset is zero. However, reordering of functions in the future could break it. Signed-off-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Acked-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2023-06-20s390/boot: fix physmem_info virtual vs physical address confusionAlexander Gordeev
Fix virtual vs physical address confusion (which currently are the same). Reviewed-by: Vasily Gorbik <gor@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2023-06-20s390/kasan: avoid short by one page shadow memoryAlexander Gordeev
Kernel Address Sanitizer uses 3 bits per byte to encode memory. That is the number of bits the start and end address of a memory range is shifted right when the corresponding shadow memory is created for that memory range. The used memory mapping routine expects page-aligned addresses, while the above described 3-bit shift might turn the shadow memory range start and end boundaries into non-page-aligned in case the size of the original memory range is less than (PAGE_SIZE << 3). As result, the resulting shadow memory range could be short on one page. Align on page boundary the start and end addresses when mapping a shadow memory range and avoid the described issue in the future. Note, that does not fix a real problem, since currently no virtual regions of size less than (PAGE_SIZE << 3) exist. Reviewed-by: Vasily Gorbik <gor@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2023-06-20s390/kasan: fix insecure W+X mapping warningAlexander Gordeev
Since commit 3b5c3f000c2e ("s390/kasan: move shadow mapping to decompressor") the decompressor establishes mappings for the shadow memory and sets initial protection attributes to RWX. The decompressed kernel resets protection to RW+NX later on. In case a shadow memory range is not aligned on page boundary (e.g. as result of mem= kernel command line parameter use), the "Checked W+X mappings: FAILED, 1 W+X pages found" warning hits. Reported-by: Vasily Gorbik <gor@linux.ibm.com> Fixes: 557b19709da9 ("s390/kasan: move shadow mapping to decompressor") Reviewed-by: Vasily Gorbik <gor@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2023-06-20s390/crash: use the correct type for memory allocationChristophe JAILLET
get_elfcorehdr_size() returns a size_t, so there is no real point to store it in a u32. Turn 'alloc_size' into a size_t. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/0756118c9058338f3040edb91971d0bfd100027b.1686688212.git.christophe.jaillet@wanadoo.fr Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2023-06-20riscv: replace deprecated scall with ecallFangrui Song
scall is a deprecated alias for ecall. ecall is used in several places, so there is no assembler compatibility concern. Signed-off-by: Fangrui Song <maskray@google.com> Link: https://lore.kernel.org/r/20230423223210.126948-1-maskray@google.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-20riscv: uprobes: Restore thread.bad_causeTiezhu Yang
thread.bad_cause is saved in arch_uprobe_pre_xol(), it should be restored in arch_uprobe_{post,abort}_xol() accordingly, otherwise the save operation is meaningless, this change is similar with x86 and powerpc. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Acked-by: Oleg Nesterov <oleg@redhat.com> Reviewed-by: Guo Ren <guoren@kernel.org> Fixes: 74784081aac8 ("riscv: Add uprobes supported") Link: https://lore.kernel.org/r/1682214146-3756-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-20riscv: mm: try VMA lock-based page fault handling firstJisheng Zhang
Attempt VMA lock-based page fault handling first, and fall back to the existing mmap_lock-based handling if that fails. A simple running the ebizzy benchmark on Lichee Pi 4A shows that PER_VMA_LOCK can improve the ebizzy benchmark by about 32.68%. In theory, the more CPUs, the bigger improvement, but I don't have any HW platform which has more than 4 CPUs. This is the riscv variant of "x86/mm: try VMA lock-based page fault handling first". Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Suren Baghdasaryan <surenb@google.com> Link: https://lore.kernel.org/r/20230523165942.2630-1-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-20x86/smp: Put CPUs into INIT on shutdown if possibleThomas Gleixner
Parking CPUs in a HLT loop is not completely safe vs. kexec() as HLT can resume execution due to NMI, SMI and MCE, which has the same issue as the MWAIT loop. Kicking the secondary CPUs into INIT makes this safe against NMI and SMI. A broadcast MCE will take the machine down, but a broadcast MCE which makes HLT resume and execute overwritten text, pagetables or data will end up in a disaster too. So chose the lesser of two evils and kick the secondary CPUs into INIT unless the system has installed special wakeup mechanisms which are not using INIT. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230615193330.608657211@linutronix.de
2023-06-20ARM: dts: at91: use generic name for shutdown controllerClaudiu Beznea
Use poweroff generic name for shdwc node to cope with device tree specifications. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20230616101646.879480-2-claudiu.beznea@microchip.com
2023-06-20x86/smp: Split sending INIT IPI out into a helper functionThomas Gleixner
Putting CPUs into INIT is a safer place during kexec() to park CPUs. Split the INIT assert/deassert sequence out so it can be reused. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Link: https://lore.kernel.org/r/20230615193330.551157083@linutronix.de
2023-06-20x86/smp: Cure kexec() vs. mwait_play_dead() breakageThomas Gleixner
TLDR: It's a mess. When kexec() is executed on a system with offline CPUs, which are parked in mwait_play_dead() it can end up in a triple fault during the bootup of the kexec kernel or cause hard to diagnose data corruption. The reason is that kexec() eventually overwrites the previous kernel's text, page tables, data and stack. If it writes to the cache line which is monitored by a previously offlined CPU, MWAIT resumes execution and ends up executing the wrong text, dereferencing overwritten page tables or corrupting the kexec kernels data. Cure this by bringing the offlined CPUs out of MWAIT into HLT. Write to the monitored cache line of each offline CPU, which makes MWAIT resume execution. The written control word tells the offlined CPUs to issue HLT, which does not have the MWAIT problem. That does not help, if a stray NMI, MCE or SMI hits the offlined CPUs as those make it come out of HLT. A follow up change will put them into INIT, which protects at least against NMI and SMI. Fixes: ea53069231f9 ("x86, hotplug: Use mwait to offline a processor, fix the legacy case") Reported-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Ashok Raj <ashok.raj@intel.com> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230615193330.492257119@linutronix.de
2023-06-20x86/smp: Use dedicated cache-line for mwait_play_dead()Thomas Gleixner
Monitoring idletask::thread_info::flags in mwait_play_dead() has been an obvious choice as all what is needed is a cache line which is not written by other CPUs. But there is a use case where a "dead" CPU needs to be brought out of MWAIT: kexec(). This is required as kexec() can overwrite text, pagetables, stacks and the monitored cacheline of the original kernel. The latter causes MWAIT to resume execution which obviously causes havoc on the kexec kernel which results usually in triple faults. Use a dedicated per CPU storage to prepare for that. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230615193330.434553750@linutronix.de
2023-06-20x86/smp: Remove pointless wmb()s from native_stop_other_cpus()Thomas Gleixner
The wmb()s before sending the IPIs are not synchronizing anything. If at all then the apic IPI functions have to provide or act as appropriate barriers. Remove these cargo cult barriers which have no explanation of what they are synchronizing. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230615193330.378358382@linutronix.de
2023-06-20x86/smp: Dont access non-existing CPUID leafTony Battersby
stop_this_cpu() tests CPUID leaf 0x8000001f::EAX unconditionally. Intel CPUs return the content of the highest supported leaf when a non-existing leaf is read, while AMD CPUs return all zeros for unsupported leafs. So the result of the test on Intel CPUs is lottery. While harmless it's incorrect and causes the conditional wbinvd() to be issued where not required. Check whether the leaf is supported before reading it. [ tglx: Adjusted changelog ] Fixes: 08f253ec3767 ("x86/cpu: Clear SME feature flag when not in use") Signed-off-by: Tony Battersby <tonyb@cybernetics.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/3817d810-e0f1-8ef8-0bbd-663b919ca49b@cybernetics.com Link: https://lore.kernel.org/r/20230615193330.322186388@linutronix.de
2023-06-20x86/smp: Make stop_other_cpus() more robustThomas Gleixner
Tony reported intermittent lockups on poweroff. His analysis identified the wbinvd() in stop_this_cpu() as the culprit. This was added to ensure that on SME enabled machines a kexec() does not leave any stale data in the caches when switching from encrypted to non-encrypted mode or vice versa. That wbinvd() is conditional on the SME feature bit which is read directly from CPUID. But that readout does not check whether the CPUID leaf is available or not. If it's not available the CPU will return the value of the highest supported leaf instead. Depending on the content the "SME" bit might be set or not. That's incorrect but harmless. Making the CPUID readout conditional makes the observed hangs go away, but it does not fix the underlying problem: CPU0 CPU1 stop_other_cpus() send_IPIs(REBOOT); stop_this_cpu() while (num_online_cpus() > 1); set_online(false); proceed... -> hang wbinvd() WBINVD is an expensive operation and if multiple CPUs issue it at the same time the resulting delays are even larger. But CPU0 already observed num_online_cpus() going down to 1 and proceeds which causes the system to hang. This issue exists independent of WBINVD, but the delays caused by WBINVD make it more prominent. Make this more robust by adding a cpumask which is initialized to the online CPU mask before sending the IPIs and CPUs clear their bit in stop_this_cpu() after the WBINVD completed. Check for that cpumask to become empty in stop_other_cpus() instead of watching num_online_cpus(). The cpumask cannot plug all holes either, but it's better than a raw counter and allows to restrict the NMI fallback IPI to be sent only the CPUs which have not reported within the timeout window. Fixes: 08f253ec3767 ("x86/cpu: Clear SME feature flag when not in use") Reported-by: Tony Battersby <tonyb@cybernetics.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/3817d810-e0f1-8ef8-0bbd-663b919ca49b@cybernetics.com Link: https://lore.kernel.org/r/87h6r770bv.ffs@tglx
2023-06-20MIPS: PCI: Convert to platform remove callback returning voidUwe Kleine-König
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() is renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. While destroying alignment of the assignments in bridge_driver, do it consistently and use a single space before =. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: Loongson64: loongson3_defconfig: Enable amdgpu drm driverSui Jingfeng
As it's usuable on LS3A4000 platform. Tested with RX550, glmark2 got about 4235 score. Signed-off-by: Sui Jingfeng <suijingfeng@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: Mark core_vpe_count() as __initNathan Chancellor
After commit 96cb8ae28c65 ("MIPS: Rework smt cmdline parameters"), modpost complains when building with clang: WARNING: modpost: vmlinux.o: section mismatch in reference: core_vpe_count (section: .text) -> smp_max_threads (section: .init.data) This warning occurs when core_vpe_count() is not inlined, as it appears that a non-init function is referring to an init symbol. However, this is not a problem in practice because core_vpe_count() is only called from __init functions, cps_smp_setup() and cps_prepare_cpus(). Resolve the warning by marking core_vpe_count() as __init, as it is only called in an init context so it can refer to init functions and symbols and have its memory freed on boot. Fixes: 96cb8ae28c65 ("MIPS: Rework smt cmdline parameters") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: mm: Remove special handling for OCTEON CPUsThomas Bogendoerfer
Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs, so we don't need the extra switch cases for them. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20powerpc/mm/book3s64: Use pmdp_ptep helper instead of typecasting.Aneesh Kumar K.V
No functional change in this patch. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Tested-by: Sachin Sant <sachinp@linux.ibm.com <mailto:sachinp@linux.ibm.com>> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230616110826.344417-2-aneesh.kumar@linux.ibm.com
2023-06-20RISC-V: KVM: Remove unneeded semicolonYang Li
./arch/riscv/kvm/aia_imsic.c:94:2-3: Unneeded semicolon ./arch/riscv/kvm/aia_imsic.c:134:2-3: Unneeded semicolon ./arch/riscv/kvm/aia_imsic.c:173:2-3: Unneeded semicolon ./arch/riscv/kvm/aia_imsic.c:210:2-3: Unneeded semicolon ./arch/riscv/kvm/aia_imsic.c:296:2-3: Unneeded semicolon ./arch/riscv/kvm/aia_imsic.c:354:2-3: Unneeded semicolon ./arch/riscv/kvm/aia_device.c:105:4-5: Unneeded semicolon ./arch/riscv/kvm/aia_device.c:166:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5569 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-06-20RISC-V: KVM: Allow Svnapot extension for Guest/VMAnup Patel
We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Svnapot extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-06-19riscv: mm: Pre-allocate PGD entries for vmalloc/modules areaBjörn Töpel
The RISC-V port requires that kernel PGD entries are to be synchronized between MMs. This is done via the vmalloc_fault() function, that simply copies the PGD entries from init_mm to the faulting one. Historically, faulting in PGD entries have been a source for both bugs [1], and poor performance. One way to get rid of vmalloc faults is by pre-allocating the PGD entries. Pre-allocating the entries potientially wastes 64 * 4K (65 on SV39). The pre-allocation function is pulled from Jörg Rödel's x86 work, with the addition of 3-level page tables (PMD allocations). The pmd_alloc() function needs the ptlock cache to be initialized (when split page locks is enabled), so the pre-allocation is done in a RISC-V specific pgtable_cache_init() implementation. Pre-allocate the kernel PGD entries for the vmalloc/modules area, but only for 64b platforms. Link: https://lore.kernel.org/lkml/20200508144043.13893-1-joro@8bytes.org/ # [1] Signed-off-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20230531093817.665799-1-bjorn@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-19Merge tag 'hyperv-fixes-signed-20230619' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux Pull hyperv fixes from Wei Liu: - Fix races in Hyper-V PCI controller (Dexuan Cui) - Fix handling of hyperv_pcpu_input_arg (Michael Kelley) - Fix vmbus_wait_for_unload to scan present CPUs (Michael Kelley) - Call hv_synic_free in the failure path of hv_synic_alloc (Dexuan Cui) - Add noop for real mode handlers for virtual trust level code (Saurabh Sengar) * tag 'hyperv-fixes-signed-20230619' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: PCI: hv: Add a per-bus mutex state_lock Revert "PCI: hv: Fix a timing issue which causes kdump to fail occasionally" PCI: hv: Remove the useless hv_pcichild_state from struct hv_pci_dev PCI: hv: Fix a race condition in hv_irq_unmask() that can cause panic PCI: hv: Fix a race condition bug in hv_pci_query_relations() arm64/hyperv: Use CPUHP_AP_HYPERV_ONLINE state to fix CPU online sequencing x86/hyperv: Fix hyperv_pcpu_input_arg handling when CPUs go online/offline Drivers: hv: vmbus: Fix vmbus_wait_for_unload() to scan present CPUs Drivers: hv: vmbus: Call hv_synic_free() if hv_synic_alloc() fails x86/hyperv/vtl: Add noop for realmode pointers
2023-06-19watchdog/hardlockup: define HARDLOCKUP_DETECTOR_ARCHPetr Mladek
The HAVE_ prefix means that the code could be enabled. Add another variable for HAVE_HARDLOCKUP_DETECTOR_ARCH without this prefix. It will be set when it should be built. It will make it compatible with the other hardlockup detectors. The change allows to clean up dependencies of PPC_WATCHDOG and HAVE_HARDLOCKUP_DETECTOR_PERF definitions for powerpc. As a result HAVE_HARDLOCKUP_DETECTOR_PERF has the same dependencies on arm, x86, powerpc architectures. Link: https://lkml.kernel.org/r/20230616150618.6073-7-pmladek@suse.com Signed-off-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19watchdog/sparc64: define HARDLOCKUP_DETECTOR_SPARC64Petr Mladek
The HAVE_ prefix means that the code could be enabled. Add another variable for HAVE_HARDLOCKUP_DETECTOR_SPARC64 without this prefix. It will be set when it should be built. It will make it compatible with the other hardlockup detectors. Before, it is far from obvious that the SPARC64 variant is actually used: $> make ARCH=sparc64 defconfig $> grep HARDLOCKUP_DETECTOR .config CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y CONFIG_HAVE_HARDLOCKUP_DETECTOR_SPARC64=y After, it is more clear: $> make ARCH=sparc64 defconfig $> grep HARDLOCKUP_DETECTOR .config CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y CONFIG_HAVE_HARDLOCKUP_DETECTOR_SPARC64=y CONFIG_HARDLOCKUP_DETECTOR_SPARC64=y Link: https://lkml.kernel.org/r/20230616150618.6073-6-pmladek@suse.com Signed-off-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19watchdog/hardlockup: make HAVE_NMI_WATCHDOG sparc64-specificPetr Mladek
There are several hardlockup detector implementations and several Kconfig values which allow selection and build of the preferred one. CONFIG_HARDLOCKUP_DETECTOR was introduced by the commit 23637d477c1f53acb ("lockup_detector: Introduce CONFIG_HARDLOCKUP_DETECTOR") in v2.6.36. It was a preparation step for introducing the new generic perf hardlockup detector. The existing arch-specific variants did not support the to-be-created generic build configurations, sysctl interface, etc. This distinction was made explicit by the commit 4a7863cc2eb5f98 ("x86, nmi_watchdog: Remove ARCH_HAS_NMI_WATCHDOG and rely on CONFIG_HARDLOCKUP_DETECTOR") in v2.6.38. CONFIG_HAVE_NMI_WATCHDOG was introduced by the commit d314d74c695f967e105 ("nmi watchdog: do not use cpp symbol in Kconfig") in v3.4-rc1. It replaced the above mentioned ARCH_HAS_NMI_WATCHDOG. At that time, it was still used by three architectures, namely blackfin, mn10300, and sparc. The support for blackfin and mn10300 architectures has been completely dropped some time ago. And sparc is the only architecture with the historic NMI watchdog at the moment. And the old sparc implementation is really special. It is always built on sparc64. It used to be always enabled until the commit 7a5c8b57cec93196b ("sparc: implement watchdog_nmi_enable and watchdog_nmi_disable") added in v4.10-rc1. There are only few locations where the sparc64 NMI watchdog interacts with the generic hardlockup detectors code: + implements arch_touch_nmi_watchdog() which is called from the generic touch_nmi_watchdog() + implements watchdog_hardlockup_enable()/disable() to support /proc/sys/kernel/nmi_watchdog + is always preferred over other generic watchdogs, see CONFIG_HARDLOCKUP_DETECTOR + includes asm/nmi.h into linux/nmi.h because some sparc-specific functions are needed in sparc-specific code which includes only linux/nmi.h. The situation became more complicated after the commit 05a4a95279311c3 ("kernel/watchdog: split up config options") and commit 2104180a53698df5 ("powerpc/64s: implement arch-specific hardlockup watchdog") in v4.13-rc1. They introduced HAVE_HARDLOCKUP_DETECTOR_ARCH. It was used for powerpc specific hardlockup detector. It was compatible with the perf one regarding the general boot, sysctl, and programming interfaces. HAVE_HARDLOCKUP_DETECTOR_ARCH was defined as a superset of HAVE_NMI_WATCHDOG. It made some sense because all arch-specific detectors had some common requirements, namely: + implemented arch_touch_nmi_watchdog() + included asm/nmi.h into linux/nmi.h + defined the default value for /proc/sys/kernel/nmi_watchdog But it actually has made things pretty complicated when the generic buddy hardlockup detector was added. Before the generic perf detector was newer supported together with an arch-specific one. But the buddy detector could work on any SMP system. It means that an architecture could support both the arch-specific and buddy detector. As a result, there are few tricky dependencies. For example, CONFIG_HARDLOCKUP_DETECTOR depends on: ((HAVE_HARDLOCKUP_DETECTOR_PERF || HAVE_HARDLOCKUP_DETECTOR_BUDDY) && !HAVE_NMI_WATCHDOG) || HAVE_HARDLOCKUP_DETECTOR_ARCH The problem is that the very special sparc implementation is defined as: HAVE_NMI_WATCHDOG && !HAVE_HARDLOCKUP_DETECTOR_ARCH Another problem is that the meaning of HAVE_NMI_WATCHDOG is far from clear without reading understanding the history. Make the logic less tricky and more self-explanatory by making HAVE_NMI_WATCHDOG specific for the sparc64 implementation. And rename it to HAVE_HARDLOCKUP_DETECTOR_SPARC64. Note that HARDLOCKUP_DETECTOR_PREFER_BUDDY, HARDLOCKUP_DETECTOR_PERF, and HARDLOCKUP_DETECTOR_BUDDY may conflict only with HAVE_HARDLOCKUP_DETECTOR_ARCH. They depend on HARDLOCKUP_DETECTOR and it is not longer enabled when HAVE_NMI_WATCHDOG is set. Link: https://lkml.kernel.org/r/20230616150618.6073-5-pmladek@suse.com Signed-off-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19watchdog/hardlockup: declare arch_touch_nmi_watchdog() only in linux/nmi.hPetr Mladek
arch_touch_nmi_watchdog() needs a different implementation for various hardlockup detector implementations. And it does nothing when any hardlockup detector is not built at all. arch_touch_nmi_watchdog() is declared via linux/nmi.h. And it must be defined as an empty function when there is no hardlockup detector. It is done directly in this header file for the perf and buddy detectors. And it is done in the included asm/linux.h for arch specific detectors. The reason probably is that the arch specific variants build the code using another conditions. For example, powerpc64/sparc64 builds the code when CONFIG_PPC_WATCHDOG is enabled. Another reason might be that these architectures define more functions in asm/nmi.h anyway. However the generic code actually knows when the function will be implemented. It happens when some full featured or the sparc64-specific hardlockup detector is built. In particular, CONFIG_HARDLOCKUP_DETECTOR can be enabled only when a generic or arch-specific full featured hardlockup detector is available. The only exception is sparc64 which can be built even when the global HARDLOCKUP_DETECTOR switch is disabled. The information about sparc64 is a bit complicated. The hardlockup detector is built there when CONFIG_HAVE_NMI_WATCHDOG is set and CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH is not set. People might wonder whether this change really makes things easier. The motivation is: + The current logic in linux/nmi.h is far from obvious. For example, arch_touch_nmi_watchdog() is defined as {} when neither CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER nor CONFIG_HAVE_NMI_WATCHDOG is defined. + The change synchronizes the checks in lib/Kconfig.debug and in the generic code. + It is a step that will help cleaning HAVE_NMI_WATCHDOG related checks. The change should not change the existing behavior. Link: https://lkml.kernel.org/r/20230616150618.6073-4-pmladek@suse.com Signed-off-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19watchdog/hardlockup: make the config checks more straightforwardPetr Mladek
There are four possible variants of hardlockup detectors: + buddy: available when SMP is set. + perf: available when HAVE_HARDLOCKUP_DETECTOR_PERF is set. + arch-specific: available when HAVE_HARDLOCKUP_DETECTOR_ARCH is set. + sparc64 special variant: available when HAVE_NMI_WATCHDOG is set and HAVE_HARDLOCKUP_DETECTOR_ARCH is not set. The check for the sparc64 variant is more complicated because HAVE_NMI_WATCHDOG is used to #ifdef code used by both arch-specific and sparc64 specific variant. Therefore it is automatically selected with HAVE_HARDLOCKUP_DETECTOR_ARCH. This complexity is partly hidden in HAVE_HARDLOCKUP_DETECTOR_NON_ARCH. It reduces the size of some checks but it makes them harder to follow. Finally, the other temporary variable HARDLOCKUP_DETECTOR_NON_ARCH is used to re-compute HARDLOCKUP_DETECTOR_PERF/BUDDY when the global HARDLOCKUP_DETECTOR switch is enabled/disabled. Make the logic more straightforward by the following changes: + Better explain the role of HAVE_HARDLOCKUP_DETECTOR_ARCH and HAVE_NMI_WATCHDOG in comments. + Add HAVE_HARDLOCKUP_DETECTOR_BUDDY so that there is separate HAVE_* for all four hardlockup detector variants. Use it in the other conditions instead of SMP. It makes it clear that it is about the buddy detector. + Open code HAVE_HARDLOCKUP_DETECTOR_NON_ARCH in HARDLOCKUP_DETECTOR and HARDLOCKUP_DETECTOR_PREFER_BUDDY. It helps to understand the conditions between the four hardlockup detector variants. + Define the exact conditions when HARDLOCKUP_DETECTOR_PERF/BUDDY can be enabled. It explains the dependency on the other hardlockup detector variants. Also it allows to remove HARDLOCKUP_DETECTOR_NON_ARCH by using "imply". It triggers re-evaluating HARDLOCKUP_DETECTOR_PERF/BUDDY when the global HARDLOCKUP_DETECTOR switch is changed. + Add dependency on HARDLOCKUP_DETECTOR so that the affected variables disappear when the hardlockup detectors are disabled. Another nice side effect is that HARDLOCKUP_DETECTOR_PREFER_BUDDY value is not preserved when the global switch is disabled. The user has to make the decision again when it gets re-enabled. Link: https://lkml.kernel.org/r/20230616150618.6073-3-pmladek@suse.com Signed-off-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19watchdog/hardlockup: HAVE_NMI_WATCHDOG must implement ↵Douglas Anderson
watchdog_hardlockup_probe() Right now there is one arch (sparc64) that selects HAVE_NMI_WATCHDOG without selecting HAVE_HARDLOCKUP_DETECTOR_ARCH. Because of that one architecture, we have some special case code in the watchdog core to handle the fact that watchdog_hardlockup_probe() isn't implemented. Let's implement watchdog_hardlockup_probe() for sparc64 and get rid of the special case. As a side effect of doing this, code inspection tells us that we could fix a minor bug where the system won't properly realize that NMI watchdogs are disabled. Specifically, on powerpc if CONFIG_PPC_WATCHDOG is turned off the arch might still select CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH which selects CONFIG_HAVE_NMI_WATCHDOG. Since CONFIG_PPC_WATCHDOG was off then nothing will override the "weak" watchdog_hardlockup_probe() and we'll fallback to looking at CONFIG_HAVE_NMI_WATCHDOG. Link: https://lkml.kernel.org/r/20230526184139.2.Ic6ebbf307ca0efe91f08ce2c1eb4a037ba6b0700@changeid Signed-off-by: Douglas Anderson <dianders@chromium.org> Suggested-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Petr Mladek <pmladek@suse.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19sh: move the ARCH_DMA_MINALIGN definition to asm/cache.hCatalin Marinas
The sh architecture defines ARCH_DMA_MINALIGN in asm/page.h. Move it to asm/cache.h to allow a generic ARCH_DMA_MINALIGN definition in linux/cache.h without redefine errors/warnings. Link: https://lkml.kernel.org/r/20230613155245.1228274-4-catalin.marinas@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: kernel test robot <lkp@intel.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Vlastimil Babka <vbabka@suse.cz> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19microblaze: move the ARCH_{DMA,SLAB}_MINALIGN definitions to asm/cache.hCatalin Marinas
The microblaze architecture defines ARCH_DMA_MINALIGN in asm/page.h. Move it to asm/cache.h to allow a generic ARCH_DMA_MINALIGN definition in linux/cache.h without redefine errors/warnings. While at it, also move ARCH_SLAB_MINALIGN to asm/cache.h for consistency. Link: https://lkml.kernel.org/r/20230613155245.1228274-3-catalin.marinas@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Cc: kernel test robot <lkp@intel.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Rich Felker <dalias@libc.org> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19powerpc: move the ARCH_DMA_MINALIGN definition to asm/cache.hCatalin Marinas
Patch series "Move the ARCH_DMA_MINALIGN definition to asm/cache.h". The ARCH_KMALLOC_MINALIGN reduction series defines a generic ARCH_DMA_MINALIGN in linux/cache.h: https://lore.kernel.org/r/20230612153201.554742-2-catalin.marinas@arm.com/ Unfortunately, this causes a duplicate definition warning for microblaze, powerpc (32-bit only) and sh as these architectures define ARCH_DMA_MINALIGN in a different file than asm/cache.h. Move the macro to asm/cache.h to avoid this issue and also bring them in line with the other architectures. This patch (of 3): The powerpc architecture defines ARCH_DMA_MINALIGN in asm/page_32.h and only if CONFIG_NOT_COHERENT_CACHE is enabled (32-bit platforms only). Move this macro to asm/cache.h to allow a generic ARCH_DMA_MINALIGN definition in linux/cache.h without redefine errors/warnings. Link: https://lkml.kernel.org/r/20230613155245.1228274-1-catalin.marinas@arm.com Link: https://lkml.kernel.org/r/20230613155245.1228274-2-catalin.marinas@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202306131053.1ybvRRhO-lkp@intel.com/ Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Rich Felker <dalias@libc.org> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-06-19arm64: enable ARCH_WANT_KMALLOC_DMA_BOUNCE for arm64Catalin Marinas
With the DMA bouncing of unaligned kmalloc() buffers now in place, enable it for arm64 to allow the kmalloc-{8,16,32,48,96} caches. In addition, always create the swiotlb buffer even when the end of RAM is within the 32-bit physical address range (the swiotlb buffer can still be disabled on the kernel command line). Link: https://lkml.kernel.org/r/20230612153201.554742-18-catalin.marinas@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Isaac J. Manjarres <isaacmanjarres@google.com> Cc: Will Deacon <will@kernel.org> Cc: Alasdair Kergon <agk@redhat.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Christoph Hellwig <hch@lst.de> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Jerry Snitselaar <jsnitsel@redhat.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Logan Gunthorpe <logang@deltatee.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Mike Snitzer <snitzer@kernel.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Saravana Kannan <saravanak@google.com> Cc: Vlastimil Babka <vbabka@suse.cz> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
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