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2025-07-11ARM: dts: imx6-gw: Replace license text comment with SPDX identifierBence Csókás
Replace verbatim license text with a `SPDX-License-Identifier`. The comment header mis-attributes this license to be "X11", but the license text does not include the last line "Except as contained in this notice, the name of the X Consortium shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the X Consortium.". Therefore, this license is actually equivalent to the SPDX "MIT" license (confirmed by text diffing). Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-11ARM: dts: imx6ul-kontron-sl-common: Fix QSPI NAND node nameFrieder Schrempf
Rename QSPI NAND node to 'flash@0' in order to fix the following dt-schema warning: spi-flash@0 (spi-nand): $nodename:0: 'spi-flash@0' does not match '^(flash|.*sram|nand)(@.*)?$' Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-11ARM: dts: imx6ul-kontron-sl-common: Add SPI NOR partitionsEberhard Stoll
Describe the partitions for the bootloader and the environment on the SPI NOR. While at it also fix the order of the properties in the flash node itself. Signed-off-by: Eberhard Stoll <eberhard.stoll@kontron.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-11ARM: dts: imx6ul-kontron-bl-common: Fix RTS polarity for RS485 interfaceAnnette Kobou
The polarity of the DE signal of the transceiver is active-high for sending. Therefore rs485-rts-active-low is wrong and needs to be removed to make RS485 transmissions work. Signed-off-by: Annette Kobou <annette.kobou@kontron.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Fixes: 1ea4b76cdfde ("ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-11ARM: mediatek: add MT6572 smp bring up codeMax Shevchenko
Add support for booting the secondary CPU on the MT6572 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Max Shevchenko <wctrl@proton.me> Link: https://lore.kernel.org/r/20250702-mt6572-v4-8-bde75b7ed445@proton.me Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-07-11ARM: mediatek: add board_dt_compat entry for the MT6572 SoCMax Shevchenko
Add a compatible string for the MT6572 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Max Shevchenko <wctrl@proton.me> Link: https://lore.kernel.org/r/20250702-mt6572-v4-7-bde75b7ed445@proton.me Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-07-09ARM: tegra: Add device-tree for ASUS VivoTab RT TF600TSvyatoslav Ryhel
Add device-tree for ASUS VivoTab RT TF600T, which is NVIDIA Tegra30-based tablet device with Windows RT. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Link: https://lore.kernel.org/r/20250617070320.9153-3-clamor95@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09ARM: tegra: Use I/O memcpy to write to IRAMAaron Kling
Kasan crashes the kernel trying to check boundaries when using the normal memcpy. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250522-mach-tegra-kasan-v1-1-419041b8addb@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-07arm: dts: ti: omap: Fixup pinheader typoAlbin Törnqvist
This commit fixes a typo introduced in commit ee368a10d0df ("ARM: dts: am335x-boneblack.dts: unique gpio-line-names"). gpio0_7 is located on the P9 header on the BBB. This was verified with a BeagleBone Black by toggling the pin and checking with a multimeter that it corresponds to pin 42 on the P9 header. Signed-off-by: Albin Törnqvist <albin.tornqvist@codiax.se> Link: https://lore.kernel.org/r/20250624114839.1465115-2-albin.tornqvist@codiax.se Fixes: ee368a10d0df ("ARM: dts: am335x-boneblack.dts: unique gpio-line-names") Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-07-07ARM: dts: am335x-pdu001: Fix RS-485 transceiver switchingFelix Brack
The wiring of the RS-485 transceiver of UART0 of the PDU-001 board allows sending or receiving date exclusively. In other words: no character transmitted will ever be received. Hence the tx-filter counter in the OMAP serial driver can't work correctly as it relies on receiving the transmitted characters. This in turn will prevent reception of data unless we disable the tx-filter counter. This patch disables the tx-filter counter by enabling the DTS setting rs485-rx-during-tx. This might sound like the opposite to be done but it uses the enabling of rs485-rx-during-tx not for receiving the data transmitted but for disabling the tx-fiter counter. Tested-by: Felix Brack <fb@ltec.ch> Signed-off-by: Felix Brack <fb@ltec.ch> Link: https://lore.kernel.org/r/20250529135324.182868-1-fb@ltec.ch Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-07-07ARM: dts: marvell: kirkwood: use recent scl/sda gpio bindingsWolfram Sang
We have dedictaded bindings for scl/sda nowadays. Switch away from the deprecated plain 'gpios' property. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-07-07arm: orion: use string choices helperKuninori Morimoto
We can use string choices helper, let's use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-07-07ARM: dts: imx6-karo: Replace license text comment with SPDX identifierBence Csókás
Replace verbatim license text with a `SPDX-License-Identifier` The comment header mis-attributes this license to be "X11", but the license text does not include the last line "Except as contained in this notice, the name of the X Consortium shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the X Consortium.". Therefore, this license is actually equivalent to the SPDX "MIT" license (confirmed by text diffing). Cc: Lothar Waßmann <LW@KARO-electronics.de> Acked-By: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-07Merge tag 'pm-runtime-6.17-rc1' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm into gpio/for-next Runtime PM updates related to autosuspend for 6.17 Make several autosuspend functions mark last busy stamp and update the documentation accordingly (Sakari Ailus).
2025-07-07Merge tag 'gpio-mmio-remove-bgpio-pdata-for-v6.17-rc1' into gpio/for-nextBartosz Golaszewski
Immutable branch between GPIO, MFD and ARM-SoC for v6.17-rc1 Remove struct bgpio_pdata after converting its users to generic device properties.
2025-07-07ARM: s3c: crag6410: use generic device properties for gpio-mmioBartosz Golaszewski
The GPIO device in crag6410 is registered with struct bgpio_pdata passed as platform_data to the gpio-mmio driver. We want to remove the bgpio_pdata from the kernel and the gpio-mmio driver is now also able to get the relevant values from the software node. Set up device properties and switch to using platform_device_info to register the device as platform_add_devices() doesn't allow us to pass device properties to the driver model. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20250701-gpio-mmio-pdata-v2-5-ebf34d273497@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-07ARM: omap1: ams-delta: use generic device properties for gpio-mmioBartosz Golaszewski
The two latch GPIO devices in ams-delta are registered with struct bgpio_pdata passed as platform_data to the gpio-mmio driver. We want to remove the bgpio_pdata from the kernel and the gpio-mmio driver is now also able to get the relevant values from the software node. Set up device properties and switch to using platform_device_info to register the devices as platform_add_devices() doesn't allow us to pass device properties to the driver model. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20250701-gpio-mmio-pdata-v2-4-ebf34d273497@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-07gpio: reg: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the legacy generic gpio-reg module to using them. We have to update the two legacy ARM platforms that use it at the same time as they call the set_multiple() callbacks directly (they shouldn't but it's old technical debt I suppose). Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20250623-gpiochip-set-rv-gpio-v3-1-90f0e170a846@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-05ARM: dts: microchip: sama7g5: Add cache configuration for cpu nodeMihai Sain
Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama7d65: Add cache configuration for cpu nodeMihai Sain
Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama5d4: Update the cache configuration for CPUMihai Sain
Add the memory size properties for L1 and L2 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. - L2 cache configuration with 128 KB unified cache. [root@sama5d4 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) L2: 128 KiB (1 instance) Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250625064934.4828-4-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama5d3: Update the cache configuration for CPUMihai Sain
Add the memory size properties for L1 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. [root@sama5d3 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250625064934.4828-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama5d2: Update the cache configuration for CPUMihai Sain
Add the memory size properties for L1 and L2 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. - L2 cache configuration with 128 KB unified cache. [root@sama5d2 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) L2: 128 KiB (1 instance) Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250625064934.4828-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-04ARM: dts: stm32: add stm32mp157f-dk2 board supportAmelie Delaunay
STM32MP157F-DK2 board embeds a STM32MP157F SoC. This SoC contains the same level of feature than a STM32MP157C SOC but A7 clock frequency can reach 800MHz, hence the inclusion of the newly introduced stm32mp15xf.dtsi. As for other latest STM32 MPU families, STM32MP157F-DK2 relies on OP-TEE SCMI services for SoC clock and reset controllers resources, and for PMIC, now under OP-TEE control. That's why stm32mp157f-dk2-scmi.dtsi is introduced, to move all clocks, resets and regulators to SCMI-based ones. To "disable" SCMI, just need to comment stm32mp157f-dk2-scmi.dtsi inclusion and to replace &scmi_v3v3 with &v3v3, then to disable arm_wdt and to enable i2c4 and its subnodes for PMIC support by Linux. Reconfigure usbotg for dual role with type-C support if needed. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-7-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: optee async notif interrupt for MP15 scmi variantsEtienne Carriere
Define the interrupt used by OP-TEE async notif on stm32mp15 scmi based platforms. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-5-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: use internal regulators bindings for MP15 scmi variantsAmelie Delaunay
Use the SCMI voltage domain bindings for internal regulators on stm32mp15. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-4-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkxAmelie Delaunay
Adopt generic node name 'typec' for stusb1600, which is the USB Type-C controller on stm32mp157x Discovery Kits. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-2-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCsAlexandre Torgue
This commit creates new file to manage security features and supported OPP on STM32MP15xF SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot + A7-CPU@650MHz. -Y = C means cryp IP + optee + secure boot + A7-CPU@650MHz. -Y = D means no cryp IP and no secure boot + A7-CPU@800MHz. -Y = F means cryp IP + optee + secure boot + A7-CPU@800MHz. It fullfills the initial STM32MP15x SoC diversity introduced by commit 0eda69b6c5f9 ("ARM: dts: stm32: Manage security diversity for STM32M15x SOCs"). Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-1-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkxOlivier Moysan
The commit 5725bce709db ("ASoC: simple-card-utils: Unify clock direction by clk_direction") corrupts the audio on STM32MP15 DK sound cards. The parent clock is not correctly set, because set_sai_ck_rate() is not executed in stm32_sai_set_sysclk() callback. This occurs because set_sysclk() is called with the wrong direction, SND_SOC_CLOCK_IN instead of SND_SOC_CLOCK_OUT. Add system-clock-direction-out property in SAI2A endpoint node of STM32MP15XX-DKX device tree, to specify the MCLK clock direction. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Link: https://lore.kernel.org/r/20250521150418.488152-1-olivier.moysan@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: Switch to new sys-off handler APIAndrew Davis
Kernel now supports chained power-off handlers. Use register_platform_power_off() that registers a platform level power-off handler. Legacy pm_power_off() will be removed once all drivers and archs are converted to the new sys-off API. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250624184245.343657-1-afd@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-04ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addressesUwe Kleine-König
The efuse device tree description already has the two labels pointing to the efuse nodes that specify the mac-addresses to be used. Wire them up to the ethernet nodes. This is enough to make barebox pick the right mac-addresses and pass them to Linux. Suggested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20250328171406.3307778-2-u.kleine-koenig@baylibre.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: aspeed: yosemite4: add gpio name for uart mux selMarshall Zhan
Add gpio line name to support multiplexed console Signed-off-by: Marshall Zhan <marshall_zhan@wiwynn.com> Link: https://patch.msgid.link/20250630073138.3315947-1-marshall_zhan@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMCFred Chen
Add linux device tree entry related to the Meta (Facebook) compute node system using an AST2600 BMC. This node is named "Santabarbara". It is a compute node with accelerator module. The system monitors voltage and temperature for the CPU, switch, and NIC components on the motherboard and switch board. Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com> Link: https://patch.msgid.link/20250625073847.4054971-3-fredchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: bletchley: enable USB PD negotiationCosmo Chou
- Enable USB Power Delivery with revision 2.0 for all sleds - Configure dual power/data roles with sink preference Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Link: https://patch.msgid.link/20250622034247.3985727-1-chou.cosmo@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodesAnkit Chauhan
Fix an obvious spelling error in the DTS file for the Lanyang BMC ("lable" -> "label"). This was reported by bugzilla a few years ago but never got fixed. Reported-by: Jens Schleusener <Jens.Schleusener@fossies.org> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=205891 Signed-off-by: Ankit Chauhan <ankitchauhan2065@gmail.com> Link: https://patch.msgid.link/20250612075057.80433-1-ankitchauhan2065@gmail.com [arj: Replace U+2192 with '->'] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add mmc healthPeter Yin
Add a GPIO expander node at address 0x13 on i2c11 bus to monitor MMC health status via a dedicated GPIO line. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-6-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: Harma: revise gpio bride pin for batteryPeter Yin
Update the GPIO bridge pin configuration for the battery circuit on the Harma platform to reflect the correct hardware design. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-5-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoringPeter Yin
Add the ADC128D818 device to I2C bus 29 to support voltage monitoring on the Harma platform. This enables accurate measurement of system voltages through the onboard ADC. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-4-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add fan board I/O expanderPeter Yin
Add GPIO I/O expander node for the fan board to detect and monitor fan board status. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-3-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add E1.S power monitorPeter Yin
Add the E1.S power monitor device node to the Harma device tree to enable power monitoring functionality for E1.S drives. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-2-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC managementPotin Lai
Add the `mctp-controller` property and MCTP nodes to enable support for frontend NIC management via PLDM over MCTP. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250611-catalina-mctp-i2c-10-15-v1-1-2a882e461ed9@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-03clk: sunxi-ng: v3s: Fix CSI SCLK clock namePaul Kocialkowski
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the documentation. Fix the name in the driver, header and device-tree. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Reviewed-By: Icenowy Zheng <uwu@icenowy.me> Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-03ARM: dts: lpc32xx: Add #pwm-cells property to the two SoC PWMsUwe Kleine-König
If these PWMs are to be used, a #pwm-cells property is necessary. The right location for that is in the SoC's dtsi file to not make machine.dts files repeat the value for each usage. Currently the machines based on nxp/lpc/lpc32xx.dtsi don't make use of the PWMs, so there are no properties to drop there. Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-03Merge tag 'arm-soc/for-6.17/devicetree' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM-based SoCs Device Tree updates for 6.17, please pull the following: - Linus makes a number of updates to the BCMBCA SoCs Device Tree files to correct UART interrupt numbers, add interrupts to the RNG block, and leverage the fact that all SoCs have the same peripherals at the same aperture - Uwe corrects the Merakia MX6X DTS file to have #pwm-cells = 3 as per the binding * tag 'arm-soc/for-6.17/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm958625-meraki-mx6x: Use #pwm-cells = <3> ARM: dts: bcm63178: Add BCMBCA peripherals ARM: dts: bcm63148: Add BCMBCA peripherals ARM: dts: bcm63138: Add BCMBCA peripherals ARM: dts: bcm6878: Add BCMBCA peripherals ARM: dts: bcm6855: Add BCMBCA peripherals ARM: dts: bcm6846: Add interrupt to RNG dt-bindings: rng: r200: Add interrupt property ARM: dts: bcm6878: Correct UART0 IRQ number Link: https://lore.kernel.org/r/20250630190216.1518354-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-03Merge tag 'renesas-dts-for-v6.17-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.17 - Add SPI FLASH, camera, and Ethernet support on the RZ/G3E SoC and/or the RZ/G3E SoM and SMARC Carrier-II EVK development board, - Add Ethernet, USB2, and PMIC support on the RZ/V2H and RZ/V2N SoCs and EVK boards, - Add timer, I2C, watchdog, and GPU support on the RZ/V2N SoC and the RZ/V2N EVK board, - Add debug LED support for the RZN1D-DB development board, - Improve PCIe clock description on the Retronix Sparrow Hawk board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits) arm64: dts: renesas: r9a09g047: Add GBETH nodes arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node names arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMIC arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMIC arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMs arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock arm64: dts: renesas: r8a779g0: Describe PCIe root ports arm64: dts: renesas: ebisu: Add CAN0 support ARM: dts: renesas: r9a06g032: Add second clock input to RTC arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 support arm64: dts: renesas: r9a09g056: Add USB2.0 support arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTS ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDs arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support PCI/pwrctrl: Add optional slot clock for PCI slots arm64: dts: renesas: r9a09g057: Add USB2.0 support arm64: dts: renesas: r9a09g047e57-smarc: Enable CRU, CSI support arm64: dts: renesas: renesas-smarc2: Enable I2C0 node arm64: dts: renesas: r9a09g047e57-smarc: Add I2C0 pincontrol arm64: dts: renesas: r9a09g047: Add CRU, CSI2 nodes ... Link: https://lore.kernel.org/r/cover.1751026664.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-02fs: introduce file_getattr and file_setattr syscallsAndrey Albershteyn
Introduce file_getattr() and file_setattr() syscalls to manipulate inode extended attributes. The syscalls takes pair of file descriptor and pathname. Then it operates on inode opened accroding to openat() semantics. The struct file_attr is passed to obtain/change extended attributes. This is an alternative to FS_IOC_FSSETXATTR ioctl with a difference that file don't need to be open as we can reference it with a path instead of fd. By having this we can manipulated inode extended attributes not only on regular files but also on special ones. This is not possible with FS_IOC_FSSETXATTR ioctl as with special files we can not call ioctl() directly on the filesystem inode using fd. This patch adds two new syscalls which allows userspace to get/set extended inode attributes on special files by using parent directory and a path - *at() like syscall. CC: linux-api@vger.kernel.org CC: linux-fsdevel@vger.kernel.org CC: linux-xfs@vger.kernel.org Signed-off-by: Andrey Albershteyn <aalbersh@kernel.org> Link: https://lore.kernel.org/20250630-xattrat-syscall-v6-6-c4e3bc35227b@kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-07-02ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definitionPaul Kocialkowski
The V3 supports RGB666 LCD output on PD pins, which are not available on the V3s package. Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201534.815513-2-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-02ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definitionPaul Kocialkowski
The V3s (and other packages) supports RGB666 LCD output on PE pins. Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201534.815513-1-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA GTW boardDario Binacchi
Support Engicam MicroGEA GTW board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Buttons - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA RMM boardDario Binacchi
Support Engicam MicroGEA RMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 17:12:30 +0000