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2013-02-11arm: socfpga: Add entries to enable make dtbs socfpgaDinh Nguyen
Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Tested-by: Pavel Machek <pavel@denx.de> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11arm: socfpga: Add new device tree source for actual socfpga HWDinh Nguyen
Up to this point, support for socfpga has only been on a virtual platform. Now that actual hardware is available, we add the appropriate device tree source files. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Tested-by: Pavel Machek <pavel@denx.de> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11ARM: msm: proc_comm_boot_wait should not be __initArnd Bergmann
msm_smd_probe is a driver probe function and may get called after the __init time, so it must not call any __init function, as the link-time warning reports. Take away the __init annotation on proc_comm_boot_wait to fix this. Without this patch, building msm_defconfig results in: WARNING: vmlinux.o(.text+0xb048): Section mismatch in reference from the function msm_smd_probe() to the function .init.text:proc_comm_boot_wait() The function msm_smd_probe() references the function __init proc_comm_boot_wait(). This is often because msm_smd_probe lacks a __init annotation or the annotation of proc_comm_boot_wait is wrong. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Daniel Walker <c_dwalke@quicinc.com> Cc: linux-arm-msm@vger.kernel.org Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11ARM: KVM: arch_timers: Wire the init code and config optionMarc Zyngier
It is now possible to select CONFIG_KVM_ARM_TIMER to enable the KVM architected timer support. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: arch_timers: Add timer world switchMarc Zyngier
Do the necessary save/restore dance for the timers in the world switch code. In the process, allow the guest to read the physical counter, which is useful for its own clock_event_device. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: arch_timers: Add guest timer core supportMarc Zyngier
Add some the architected timer related infrastructure, and support timer interrupt injection, which can happen as a resultof three possible events: - The virtual timer interrupt has fired while we were still executing the guest - The timer interrupt hasn't fired, but it expired while we were doing the world switch - A hrtimer we programmed earlier has fired Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11Merge branch 'for-arm-soc/arch-timers' of ↵Marc Zyngier
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into kvm-arm/timer
2013-02-11ARM: KVM: Add VGIC configuration optionMarc Zyngier
It is now possible to select the VGIC configuration option. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: VGIC initialisation codeMarc Zyngier
Add the init code for the hypervisor, the virtual machine, and the virtual CPUs. An interrupt handler is also wired to allow the VGIC maintenance interrupts, used to deal with level triggered interrupts and LR underflows. A CPU hotplug notifier is registered to disable/enable the interrupt as requested. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: VGIC control interface world switchMarc Zyngier
Enable the VGIC control interface to be save-restored on world switch. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: VGIC interrupt injectionMarc Zyngier
Plug the interrupt injection code. Interrupts can now be generated from user space. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: vgic: retire queued, disabled interruptsMarc Zyngier
An interrupt may have been disabled after being made pending on the CPU interface (the classic case is a timer running while we're rebooting the guest - the interrupt would kick as soon as the CPU interface gets enabled, with deadly consequences). The solution is to examine already active LRs, and check the interrupt is still enabled. If not, just retire it. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: VGIC virtual CPU interface managementMarc Zyngier
Add VGIC virtual CPU interface code, picking pending interrupts from the distributor and stashing them in the VGIC control interface list registers. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: VGIC distributor handlingMarc Zyngier
Add the GIC distributor emulation code. A number of the GIC features are simply ignored as they are not required to boot a Linux guest. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: VGIC accept vcpu and dist base addresses from user spaceChristoffer Dall
User space defines the model to emulate to a guest and should therefore decide which addresses are used for both the virtual CPU interface directly mapped in the guest physical address space and for the emulated distributor interface, which is mapped in software by the in-kernel VGIC support. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: Initial VGIC infrastructure codeMarc Zyngier
Wire the basic framework code for VGIC support and the initial in-kernel MMIO support code for the VGIC, used for the distributor emulation. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: KVM: Keep track of currently running vcpusMarc Zyngier
When an interrupt occurs for the guest, it is sometimes necessary to find out which vcpu was running at that point. Keep track of which vcpu is being run in kvm_arch_vcpu_ioctl_run(), and allow the data to be retrieved using either: - kvm_arm_get_running_vcpu(): returns the vcpu running at this point on the current CPU. Can only be used in a non-preemptible context. - kvm_arm_get_running_vcpus(): returns the per-CPU variable holding the running vcpus, usable for per-CPU interrupts. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11KVM: ARM: Introduce KVM_ARM_SET_DEVICE_ADDR ioctlChristoffer Dall
On ARM some bits are specific to the model being emulated for the guest and user space needs a way to tell the kernel about those bits. An example is mmio device base addresses, where KVM must know the base address for a given device to properly emulate mmio accesses within a certain address range or directly map a device with virtualiation extensions into the guest address space. We make this API ARM-specific as we haven't yet reached a consensus for a generic API for all KVM architectures that will allow us to do something like this. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11ARM: mach-virt: fixup machine descriptor after removal of sys_timerWill Deacon
Now that sys_timer has been removed, update the mach-virt machine descriptor to use a direct pointer to its timer_init function. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11ARM: 7643/1: sched: correct update_sched_clock()Joonsoo Kim
If we want load epoch_cyc and epoch_ns atomically, we should update epoch_cyc_copy first of all. This notify reader that updating is in progress. If we update epoch_cyc first like as current implementation, there is subtle error case. Look at the below example. <Initial Condition> cyc = 9 ns = 900 cyc_copy = 9 == CASE 1 == <CPU A = reader> <CPU B = updater> write cyc = 10 read cyc = 10 read ns = 900 write ns = 1000 write cyc_copy = 10 read cyc_copy = 10 output = (10, 900) == CASE 2 == <CPU A = reader> <CPU B = updater> read cyc = 9 write cyc = 10 write ns = 1000 read ns = 1000 read cyc_copy = 9 write cyc_copy = 10 output = (9, 1000) If atomic read is ensured, output should be (9, 900) or (10, 1000). But, output in example case are not. So, change updating sequence in order to correct this problem. Cc: <stable@vger.kernel.org> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-11Merge branch 'for-arm-soc/virt/mach' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/virt From Will Deacon, this lays the foundation for a basic virtualzed machine type. * 'for-arm-soc/virt/mach' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: ARM: mach-virt: add SMP support using PSCI ARM: Dummy Virtual Machine platform support Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11Merge branch 'depends/cleanup' into next/virtOlof Johansson
2013-02-11Merge tag 'omap-devel-b-for-3.9' of ↵Tony Lindgren
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.9/pm-wfi-take2 On OMAP2+ devices, standardize and clean up WFI entry and WFI blocking. Basic test logs are available here: http://www.pwsan.com/omap/testlogs/wfi_devel_a_3.9/20130208085027/ Conflicts: arch/arm/mach-omap2/pm24xx.c
2013-02-11Merge branch 'depends/rmk-psci' into next/virtOlof Johansson
2013-02-11Merge branch 'irqchip/gic-vic-move' into next/virtOlof Johansson
2013-02-11Merge branch 'for-arm-soc/arch-timers' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/virt From Will Deacon: This set of changes moves the arch-timer driver out from arch/arm/ and into drivers/clocksource and unifies the new driver with the arm64 copy. * 'for-arm-soc/arch-timers' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: ARM: arch_timers: switch to physical timers if HYP mode is available Documentation: Add ARMv8 to arch_timer devicetree arm64: move from arm_generic to arm_arch_timer arm64: arm_generic: prevent reading stale time arm: arch_timer: move core to drivers/clocksource arm: arch_timer: add arch_counter_set_user_access arm: arch_timer: divorce from local_timer api arm: arch_timer: add isbs to register accessors arm: arch_timer: factor out register accessors arm: arch_timer: split cntfrq accessor arm: arch_timer: standardise counter reading arm: arch_timer: use u64/u32 for register data arm: arch_timer: remove redundant available check arm: arch_timer: balance device_node refcounting Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11Merge branch 'for-rmk/broadcast' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/virt * 'for-rmk/broadcast' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: arm: Add generic timer broadcast support arm: Use generic timer broadcast receiver clockevents: Add generic timer broadcast function clockevents: Add generic timer broadcast receiver
2013-02-11Merge branch 'for-rmk/virt/kvm/core' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/virt * 'for-rmk/virt/kvm/core' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: KVM: ARM: Add maintainer entry for KVM/ARM KVM: ARM: Power State Coordination Interface implementation KVM: ARM: Handle I/O aborts KVM: ARM: Handle guest faults in KVM KVM: ARM: VFP userspace interface KVM: ARM: Demux CCSIDR in the userspace API KVM: ARM: User space API for getting/setting co-proc registers KVM: ARM: Emulation framework and CP15 emulation KVM: ARM: World-switch implementation KVM: ARM: Inject IRQs and FIQs from userspace KVM: ARM: Memory virtualization setup KVM: ARM: Hypervisor initialization KVM: ARM: Initial skeleton to compile KVM support ARM: Section based HYP idmap ARM: Add page table and page defines needed by KVM
2013-02-11Merge branch 'for-rmk/perf' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/virt * 'for-rmk/perf' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: ARM: perf: simplify __hw_perf_event_init err handling ARM: perf: remove unnecessary checks for idx < 0 ARM: perf: handle armpmu_register failing ARM: perf: don't pretend to support counting of L1I writes ARM: perf: remove redundant NULL check on cpu_pmu ARM: Use implementor and part defines from cputype.h ARM: Define CPU part numbers and implementors
2013-02-11sunxi: a13-olinuxino: Add user LED to the device treeMaxime Ripard
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-02-11Merge remote-tracking branch 'asoc/topic/simple-card' into asoc-nextMark Brown
2013-02-11Merge remote-tracking branch 'asoc/topic/samsung' into asoc-nextMark Brown
2013-02-11Merge remote-tracking branch 'asoc/topic/pxa' into asoc-nextMark Brown
2013-02-11Merge remote-tracking branch 'asoc/topic/fsi' into asoc-nextMark Brown
2013-02-10Merge branches 'sg_aess_reset_devel_3.9' and 'omap4_pm_fixes_a_3.9' into ↵Paul Walmsley
omap4_prcm_devel_a_3.9
2013-02-10ARM: OMAP4: hwmod data: Enable AESS hwmod deviceSebastien Guiriec
Enable AESS data in hwmod in order to be able to probe audio driver. Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-02-10ARM: OMAP4: hwmod data: Update AESS data with memory bank areaSebastien Guiriec
Add AESS memory bank data in hwmod in order to provide memory address information to the driver. This version also changes the AESS main clock to use a non-CLKCTRL-based functional clock. These are being removed from the clock data, since they should be handled by the IP block integration code. Without this change, the kernel crashes during boot. Thanks to Tony Lindgren for reporting this during a test merge. Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> [paul@pwsan.com: updated to change the AESS main_clk] Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-02-10ARM: OMAP4+: AESS: enable internal auto-gating during initial setupPaul Walmsley
Enable the AESS auto-gating control bit during AESS hwmod setup. This fixes the following boot warning on OMAP4: omap_hwmod: aess: _wait_target_disable failed Without this patch, the AESS IP block does not indicate to the PRCM that it is idle after it is reset. This prevents some types of SoC power management until something sets the auto-gating control bit. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Péter Ujfalusi <peter.ujfalusi@ti.com> Cc: Tony Lindgren <tony@atomide.com>
2013-02-10ARM: OMAP2+: hwmod: add enable_preprogram hookPaul Walmsley
After setup/enable, some IP blocks need some additional setting to indicate the PRCM that they are inactive until they are configured. Some examples on OMAP4 include the AESS and FSUSB IP blocks. To fix this cleanly, this patch adds another optional function pointer, enable_preprogram, to the IP block's hwmod data. The function that is pointed to is called by the hwmod code immediately after the IP block is reset. This version of the patch includes a patch description fix from Felipe. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Péter Ujfalusi <peter.ujfalusi@ti.com> Cc: Felipe Balbi <balbi@ti.com>
2013-02-10ARM: dts: add dtsi for imx6q and imx6dlShawn Guo
Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: dts: rename imx6q.dtsi to imx6qdl.dtsiShawn Guo
i.MX6 Quad and i.MX6 DualLite is similar enough to share one dtsi file, so rename imx6q.dtsi to imx6qdl.dtsi preparing for the addition of imx6dl support. Another member of i.MX6 series i.MX6 SoloLite is different enough from the other two, so it will stand as a separate dtsi. That's why we rename to imx6qdl.dtsi not imx6.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: dts: i.MX6: Add regulator delay supportAnson Huang
For ANATOP LDOs, vddcpu, vddsoc and vddpu have step time settings in the misc2 register, need to add necessary step time info for these three LDOs, then regulator driver can add necessary delay based on these settings. offset 0x170: bit [24-25]: vddcpu bit [26-27]: vddpu bit [28-29]: vddsoc field definition: 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: dts: Add device tree entry for onewire master on i.MX53Martin Fuzzey
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Evgeniy Polyakov <zbr@ioremap.net> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: i.MX53: Add clocks for i.mx53 onewire master.Martin Fuzzey
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Evgeniy Polyakov <zbr@ioremap.net> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: imx: enable imx6q-cpufreq supportShawn Guo
Update operating-points per hardware document and add support for 1 GHz and 1.2 GHz frequencies. 400 MHz, 800 MHz and 1 GHz should be supported by all i.MX6Q chips, while 1.2 GHz support needs to know from OTP fuse bit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: dts: Add apf51 basic supportLaurent Cans
Signed-off-by: Laurent Cans <laurent.cans@gmail.com> Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM i.MX6: change mxs usbphy clock usagePeter Chen
This mxs usbphy is only needs to be on after system boots up, and software never needs to control it anymore. Meanwhile, usbphy's parent needs to be notified if usb is suspend or not. So we design below mxs usbphy usage: - usbphy1_gate and usbphy2_gate: Their parents are dummy clock, we only needs to enable it after system boots up. - usbphy1 and usbphy2 Usage reserved bit for this clock, in that case, the refcount will be updated, but without hardware changing. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM: dts: imx6q: Remove silicon version from SDMA firmwareFabio Estevam
Remove silicon version from SDMA firmware. This makes it consistent with other i.MX SoCs firmware names. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM i.MX53: dts: add oftree for MBa53 baseboardSteffen Trumtrar
The MBa53 is a baseboard for the TQMA53 embedded module. This enables/adds only supported devices, i.e. it is not feature complete, because of missing drivers in mainline linux. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10ARM i.MX53: add dts for the TQ tqma53 moduleSascha Hauer
The tqma53 is an embedded module that has some features on board (e.g. emmc), but mostly just provides access to them on its interface. Going along with the imx53.dtsi, the tqma53.dtsi specifies the existing devices and their pinctrl for this module. All devices that are not on the module are disabled by default and need to be enabled in a baseboard DT. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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