| Age | Commit message (Collapse) | Author |
|---|
|
MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
capability to re-initialise clock frequencies. CPTS and RGMII has
MAIN_PLL3 as their parent which does not have this flag. While RGMII
needs this reinitialisation to default frequency to be able to get
250MHz with its divider, CPTS can not get its required 200MHz with its
divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6.
(Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side
for the same reason)
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Add support for eMMC card connected to main sdhci0 instance.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230605174551.160262-1-sabiya.d@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-15-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-14-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-13-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-12-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-11-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-10-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-9-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
eeprom node
Move the eeprom WP GPIO mux configuration to be part of the eeprom node
instead of the I2C node.
Cc: Robert Nelson <robertcnelson@gmail.com>
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Move the GPIO mux configuration needed for camera module to work to the
GPIO node instead of the I2C node.
Camera nodes are maintained as overlay files, but the common mux is
always needed to ensure that camera probes fine and ensuring the mux
is configured as part of the GPIO module allows for the multiple
overlay files to be simpler.
Cc: Robert Nelson <robertcnelson@gmail.com>
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
There are timer IO pads in the MCU domain, and in the MAIN domain.
These pads can be muxed for the related timers.
The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].
These are similar to J721e/J7200, but have different mux capabilities.
[1] http://www.ti.com/lit/zip/spruj52
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
There are 20 general purpose timers on j784s4 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
Though the count is similar to J721e/J7200/j721s2, the device IDs
and clocks used in j784s4 are different with the option of certain
clocks having options of additional clock muxes. Since there is very
minimal reuse, it is cleaner to integrate as part of SoC files itself.
The defaults are configured for clocking the timers from system
clock(HFOSC0).
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].
These are similar to J721e/J7200, but have different mux capabilities.
[1] https://www.ti.com/lit/zip/spruj28
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
There are 20 general purpose timers on j721s2 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
Though the count is similar to J721e/J7200, the device IDs and clocks
used in j721s2 are different with the option of certain clocks having
options of additional clock muxes. Since there is very minimal reuse,
it is cleaner to integrate as part of SoC files itself. The defaults
are configured for clocking the timers from system clock(HFOSC0).
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.
The multiplexing is documented in Technical Reference Manual[1] under
"Timer IO Muxing Control Registers" and "Timer IO Muxing Control
Registers", and the "Timers Overview" chapters.
We do not expose the cascade_en bit due to the racy usage of
independent 32 bit registers in-line with the timer instantiation in
the device tree. The MCU timer controls are also marked as reserved for
usage by the MCU firmware.
[1] http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
The odd numbered timers have the option of being cascaded to even
timers to create a 64 bit non-atomic counter which is racy in simple
usage, hence the clock muxes are explicitly setup to individual 32 bit
counters driven off system crystal (HFOSC) as default.
These instantiation differs from J7200 and other SoCs with the device
IDs and clocks involved for muxing.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. In addition MCU island has it's own secure proxy for
usecases involving the MCU micro controllers. These are in addition
to the one in the main domain DMSS subsystem that is used for general
purpose communication.
Describe the nodes for use with bootloaders and firmware that require
these communication paths which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since these
instances do not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. In addition MCU island has it's own secure proxy for
usecases involving the MCU micro controllers. These are in addition
to the one in the main domain DMSS subsystem that is used for general
purpose communication.
Describe the nodes for use with bootloaders and firmware that require
these communication paths which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since these
instances do not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
[nm@ti.com: Update commit message, minor updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Just use "rtc" as the nodename to better match with the bindings.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy.
Drop the duplicate and misleading ti,otap-del-sel property.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
s/mcan/can to stay in sync with bindings conventions.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI
flash with sector size of 256 KiB thus the size of the smallest partition
is chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM654 baseboard has a MT35XU512ABA
64 MiB OSPI flash with sector size of 128 KiB thus the size of the
smallest partition is chosen as 128 KiB, the partition names and
offsets are chosen according to the corresponding name and offsets
in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-5-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Describe OSPI and Hyperflash partition information through device tree,
this helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition information
in a string format. J7200 SoM has a S28 64 MiB OSPI flash with sector size
of 256 KiB thus the size of the smallest partition is chosen as 256 KiB,
the SoM also has a 64 MiB Hyperflash present on it, the partition names
and offsets are chosen according to the corresponding name and offsets
in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. J721E SK has a S28 64 MiB OSPI flash
with sector size of 256 KiB thus the size of the smallest partition is
chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Describe OSPI and QSPI flash partition information through device tree,
this helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition information
in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB
QSPI flash both with sector size of 128 KiB thus the size of the smallest
partition is chosen as 128KiB, the partition names and offsets are chosen
according to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
J784S4 has S28HS512T OSPI flash connected to OSPI0 and MT25QU512A QSPI
flash connected to OSPI1, enable support for the same. Also describe
the partition information according to the offsets in the bootloader.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-3-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS
bus for interfacing with OSPI flashes. Add the nodes to allow using
SPI flashes.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
With commit 9f6ffd0da650 ("dt-bindings: leds: Convert PCA9532 to dtschema"),
we can now add the LED controller without introducing new dtbs_check warnings.
Add missing I2C LED controller.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20230505131012.2027309-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
J721E common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-5-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory
controller, add corresponding node, pinmux and partitions for the same.
HyperBus is muxed with OSPI and only one controller can be active at a
time, therefore keep HyperBus node disabled. Bootloader will detect the
external mux state through a wkup gpio and enable the node as required.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
addition went in at around the same time and must have missed that
change so the mailboxes are not re-enabled. Do that here.
Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
eMMC tuning was incomplete earlier, so support for high speed modes was
kept disabled. Remove no-1-8-v property to enable support for high
speed modes for eMMC in J784S4 SoC.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
