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2025-06-26arm64: dts: ti: k3-j722s-evm: Fix USB gpio-hog level for Type-CSiddharth Vadapalli
According to the "GPIO Expander Map / Table" section of the J722S EVM Schematic within the Evaluation Module Design Files package [0], the GPIO Pin P05 located on the GPIO Expander 1 (I2C0/0x23) has to be pulled down to select the Type-C interface. Since commit under Fixes claims to enable the Type-C interface, update the property within "p05-hog" from "output-high" to "output-low", thereby switching from the Type-A interface to the Type-C interface. [0]: https://www.ti.com/lit/zip/sprr495 Cc: stable@vger.kernel.org Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250623100657.4082031-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-25arm64: dts: qcom: sm6115: add debug UART pinsBartosz Golaszewski
We should not rely on the bootloader to set up the pinmux of the debug UART port. Let's add pin definitions for uart4 to tlmm and bind them to the relevant device node. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250625152839.193672-1-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-25arm64: dts: exynos5433: Align i2c-gpio node names with dtschemaKrzysztof Kozlowski
New dtschema v2025.6 enforces different naming on I2C nodes thus new dtbs_check warnings appeared for I2C GPIO nodes: exynos5433-tm2.dtb: i2c-gpio-0 (i2c-gpio): $nodename:0: 'i2c-gpio-0' does not match '^i2c(@.+|-[a-z0-9]+)?$' exynos5433-tm2.dtb: i2c-gpio-0 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'amplifier@31' were unexpected) Rename the nodes to a generic i2c-[0-9]+ style with numbers continuing the SoC I2C controller indexing (3 controllers) for simplicity and obviousness, even if the SoC I2C controller is not enabled on given board. The names anyway would not conflict with SoC ones because of unit addresses. Verified with comparing two fdt (after fdtdump). Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Closes: https://lore.kernel.org/all/aCtD7BH5N_uPGkq7@shikoro/ Link: https://lore.kernel.org/r/20250612095549.77954-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-21arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PCHsun Lai
The Firefly ROC-RK3588S-PC is a SBC based on the Rockchip RK3588s SoC. Link: https://wiki.t-firefly.com/en/Station-M3/index.html The device contains the following hardware that is tested/working: - 32 or 64GB eMMC - SDMMC card slot - Realtek USB WiFi 5/BT - NVME 2242 socket - 4 or 8GB of RAM - RTL8211 GbE - USB 3.0 port - USB 2.0 port - HDMI port Signed-off-by: Hsun Lai <i@chainsx.cn> Link: https://lore.kernel.org/r/20250609113044.8846-3-i@chainsx.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-21arm64: dts: rockchip: Enable GPU on Radxa E20CJonas Karlman
Enable the Mali-450 MP2 GPU on the Radxa E20C. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250518225418.682182-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-21arm64: dts: rockchip: Add GPU node for RK3528Jonas Karlman
Add a GPU node and a opp-table for the Mali-450 MP2 in the RK3528 SoC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250518225418.682182-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-21arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"Hrushikesh Salunke
AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to "pcie0_ep" device tree node. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250610054920.2395509-1-h-salunke@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-j722s-main: Add audio-refclk0 nodeMichael Walle
Add the node for the AUDIO_EXT_REFCLK0 clock output. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618090724.1917731-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single sizeMichael Walle
Pinmux registers ends at 0x000f42ac (including). Thus, the size argument of the pinctrl-single node has to be 0x2b0. Fix it. This will fix the following error: pinctrl-single f4000.pinctrl: mux offset out of range: 0x2ac (0x2ac) Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618065239.1904953-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62a7-sk: Describe the SPI NANDMiquel Raynal
Describe the octal SPI NAND available on the low-power starter kit. The pinctrl configuration comes from TI fork. With the current mainline tree, we currently get the following performances: eraseblock write speed is 7507 KiB/s eraseblock read speed is 15802 KiB/s page write speed is 7551 KiB/s page read speed is 15609 KiB/s 2 page write speed is 7551 KiB/s 2 page read speed is 15609 KiB/s erase speed is 284444 KiB/s 2x multi-block erase speed is 512000 KiB/s Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20250613182356.1272642-1-miquel.raynal@bootlin.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-j721s2-main: Add McASP nodesJayesh Choudhary
Add McASP 0-4 instances and keep them disabled because several required properties are missing as they are board specific. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20250604104656.38752-2-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62p-verdin: Enable pull-ups on I2C_3_HDMIEmanuele Ghidoli
Enable internal bias pull-ups on the SoC-side I2C_3_HDMI that do not have external pull resistors populated on the SoM. This ensures proper default line levels. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250529102601.452859-1-ghidoliemanuele@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C busesEmanuele Ghidoli
Enable internal bias pull-ups on the SoC-side I2C buses that do not have external pull resistors populated on the SoM. This ensures proper default line levels. Cc: stable@vger.kernel.org Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250528110741.262336-1-ghidoliemanuele@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet portsWadim Egorov
For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must be supplied on CLKOUT0. Previously, our bootloader configured this clock, which is why the PRU Ethernet ports appeared to work, but the change never made it into the device tree. Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Fixes: 87adfd1ab03a ("arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes") Link: https://lore.kernel.org/r/20250521053339.1751844-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-20arm64: dts: mediatek: mt8370: Enable gpu supportLouis-Alexis Eyraud
Add a new gpu node in mt8370.dtsi to enable support for the ARM Mali G57 MC2 GPU (Valhall-JM) found on the MT8370 SoC, using the Panfrost driver. On a Mediatek Genio 510 EVK board, the panfrost driver probed with the following message: ``` panfrost 13000000.gpu: clock rate = 390000000 panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0 panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003, 80000400 panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 panfrost 13000000.gpu: shader_present=0x5 l2_present=0x1 [drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0 ``` Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20250509-mt8370-enable-gpu-v6-5-2833888cb1d3@collabora.com
2025-06-20arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 ↵Quentin Schulz
Ringneck The Haikou Video Demo adapter has a proprietary connector for a camera module which has an OV5675 camera sensor and a companion DW9714 focus lens driver. This adds support for the camera module on PX30 Ringneck module fitted on a Haikou devkit with the Haikou Video Demo adapter. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250610-ringneck-haikou-video-demo-cam-v2-3-de1bf87e0732@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-20arm64: dts: rockchip: add label to first port of ISP on px30Quentin Schulz
This will make it slightly easier for Device Trees (and Overlays) to link the ISP controller to a video input such as a CSI camera while also bringing it closer to what's been done already for the DSI controller. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250610-ringneck-haikou-video-demo-cam-v2-2-de1bf87e0732@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-20arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISPQuentin Schulz
dtc complains with the following message for DTSes which use the ISP: arch/arm64/boot/dts/rockchip/px30.dtsi:1272.19-1276.6: Warning (graph_child_address): /isp@ff4a0000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary Typically, it is expected from the device DTS(I) to update the SoC DTSI nodes if they have more than one endpoint, so let's assume there's only one endpoint in port@0 by default, instead of forcing board DTS(I)s to /delete-property/ address-cells and size-cells to make dtc happy. Because PX30 PP1516/EVB's endpoint@0 is the only endpoint and considering its parent node now has no address-cells property, dtc complains (same messages for PX30 EVB): arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi:447.29-451.6: Warning (avoid_default_addr_size): /isp@ff4a0000/ports/port@0/endpoint@0: Relying on default #address-cells value arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi:447.29-451.6: Warning (avoid_default_addr_size): /isp@ff4a0000/ports/port@0/endpoint@0: Relying on default #size-cells value arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dtb: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size' arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dtb: Warning (unique_unit_address_if_enabled): Failed prerequisite 'avoid_default_addr_size' arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi:447.29-451.6: Warning (graph_endpoint): /isp@ff4a0000/ports/port@0/endpoint@0: graph node '#address-cells' is -1, must be 1 arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi:447.29-451.6: Warning (graph_endpoint): /isp@ff4a0000/ports/port@0/endpoint@0: graph node '#size-cells' is -1, must be 0 arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dtb: Warning (graph_child_address): Failed prerequisite 'graph_endpoint' so we fix that by removing the reg property. dtc still complains (same messages for PX30 EVB): arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi:447.29-450.6: Warning (unit_address_vs_reg): /isp@ff4a0000/ports/port@0/endpoint@0: node has a unit name, but no reg or ranges property so we also remove the @0 suffix off the node name. Fixes: 8df7b4537dfb ("arm64: dts: rockchip: add isp node for px30") Fixes: 474a77395be2 ("arm64: dts: rockchip: hook up camera on px30-evb") Fixes: 56198acdbf0d ("arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250610-ringneck-haikou-video-demo-cam-v2-1-de1bf87e0732@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-20arm64: dts: s32g: add RTC nodeCiprian Marian Costea
The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from system suspend. Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: Add DSPI entries for S32G platformsLarisa Grigore
S32G3 and S32G2 have the same 6 SPI devices, add the DT entries. Devices are all the same except spi0 has 8 chip selects instead of 5. Clock settings for the chip rely on ATF Firmware [1]. [1]: https://github.com/nxp-auto-linux/arm-trusted-firmware Co-developed-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: freescale: imx93-phyboard-segin: Set ethernet1 aliasPrimoz Fiser
Set ethernet1 alias to EQOS interface on phyBOARD-Segin-i.MX93 marking it the secondary networking interface. The primary ethernet0 interface is already set by the SoM include file (imx93-phycore-som.dtsi). Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: freescale: imx93-phycore-som: Move ethernet0 alias to SoMPrimoz Fiser
Move alias for ethernet0 interface to the phyCORE-i.MX93 SoM include file. The reason behind it is that the physical location of the PHY chip connected to FEC interface is on the SoM itself and alias thus belongs into the SoM device-tree. Consequently, it can be used by all boards based on the phyCORE-i.MX93 SoM (phyBOARD-Segin and phyBOARD-Nash). This also enables us to mark FEC interface as the primary / first for networking in the bootloader and systemd (predictable interface names). Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: tqma8mpql: Add EASRC supportAlexander Stein
Enable EASRC support in tlv320aic32x4 sound card. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: tqma8mnql: Add EASRC supportAlexander Stein
Enable EASRC support in tlv320aic32x4 sound card. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline DisplayMaud Spierings
Add the BOE av123z7m-n17 variant of the Moduline Display, this variant comes with a 12.3" 1920x720 display. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline DisplayMaud Spierings
Add the BOE av101hdt-a10 variant of the Moduline Display, this variant comes with a 10.1 1280x720 display with a touchscreen (not working in mainline). Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: freescale: Add the GOcontroll Moduline Display baseboardMaud Spierings
The Moduline Display platform is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. The base Moduline Display board includes a board-to-board connector with various busses to enable adding new display types required by the application. It includes 2 Moduline IO module slots, a simple mono codec/amplifier, a four channel adc, 2 CAN busses, an RTC and optional wifi/bluetooth. busses to the display adapter include: - 4 lane LVDS - 4 lane MIPI-DSI - 4 lane MIPI-CSI - HDMI 2.0a - USB 2.0 - I2S - I2C - SPI Also a couple of GPIO and PWM pins for controlling various ICs on the display adapter board. Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMMaud Spierings
The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has 2 GB of ram and 8 GB of eMMC storage on board. Add it to enable boards based on this Module Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: imx8mp: Add pinctrl config definitionsMaud Spierings
Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this register is written in the dts, these values are not obvious. Add defines which describe the fields of this register which can be or-ed together to produce readable settings. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-20arm64: dts: rockchip: Add power controller for RK3528Jonas Karlman
Add power-domain nodes for the power controller on RK3528. Only PD_GPU can fully be powered down. PD_RKVDEC, PD_RKVENC, PD_VO and PD_VPU are idle only power domains used by miscellaneous devices. Because multiple of the miscellaneous device types currently complain about the use of a power-domains prop, only PD_GPU is enabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250518220707.669515-5-jonas@kwiboo.se [changed to using numeric values, until the next merge-window] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: enable USB on Sige5Nicolas Frattaroli
The ArmSoM Sige5 has several USB ports: a Type-A USB 3 port (USB2 lines going through a hub), a Type-A USB 2.0 port (also going through a hub), a Type-C DC input port that has absolutely no USB data connection and a Type-C port with USB3.2 Gen1x1 that's also the maskrom programming port. Enable these ports, and set the device role to be host for the host ports. The data capable Type-C USB port uses a fusb302 for data role switching. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250619-rk3576-sige5-usb-v5-2-9069a7e750e1@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: list all CPU supplies on ArmSoM Sige5Alexey Charkov
List both CPU supply regulators which drive the little and big CPU clusters, respectively, so that cpufreq can pick them up. Without this patch the cpufreq governor attempts to raise the big CPU frequency under high load, while its supply voltage stays at 850000 uV. This causes system instability and, in my case, random reboots. With this patch, supply voltages are adjusted in step with frequency changes from 700000-737000 uV in idle to 950000 uV under full load, and the system appears to be stable. While at this, list all CPU supplies for completeness. Cc: stable@vger.kernel.org Fixes: 40f742b07ab2 ("arm64: dts: rockchip: Add rk3576-armsom-sige5 board") Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-1-3bb31b02623c@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2Alexey Charkov
Add support for the Broadcom based WiFi/Bluetooth module (BW3752-50B1) found in ArmSoM Sige5 boards version 1.2. This includes SDIO connected WiFi with OOB interrupt support, as well as UART connected Bluetooth with its respective interrupts. PCM support for Bluetooth SCO audio is left out for now. It is connected to SAI2 in M0 pin mode in case someone needs to enable it. Note that v1.1 boards used a Realtek based module which is incompatible with these DT nodes, so v1.1 would need a different overlay. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-4-3bb31b02623c@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5Alexey Charkov
ArmSoM Sige5 uses a soldered-on WiFi/BT module with WiFi on SDIO and BT on UART. However, board v1.1 uses a Realtek based BL-M8852BS2, while v1.2 uses a Broadcom based BW3752-50B1. They use the same pins and controllers, but require different DT properties to enable. Thankfully, the WiFi part at least works without explicitly listing it in the device tree, albeit without OOB interrupt functionality. Add required device tree nodes that do not depend on the board version so that at least the WiFi module can appear on the SDIO bus. WiFi OOB interrupt and Bluetooth function support are not enabled here, as they require module specific properties. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-3-3bb31b02623c@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: add SDIO controller on RK3576Alexey Charkov
RK3576 has one more SD/MMC controller than are currently listed in its .dtsi, with the missing one intended as an SDIO controller. Add the missing node (tested with the onboard WiFi module on ArmSoM Sige5 v1.2) Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-2-3bb31b02623c@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10Andy Yan
Enable gpu for rk3576 evb. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20250618063609.690332-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: Update the PinePhone Pro panel descriptionOlivier Benjamin
Fix a few issues in the panel section of the PinePhone Pro DTS: - add the second part of the Himax HX8394 LCD panel controller compatible - as proposed by Diederik de Haas, reuse the mipi_out and ports definitions from rk3399-base.dtsi instead of redefining them - add a pinctrl for the LCD_RST signal for LCD1, derived from LCD1_RST, which is on GPIO4_D1, as documented on pages 11 and 16 of the PinePhone Pro schematic Signed-off-by: Olivier Benjamin <olivier.benjamin@bootlin.com> Reviewed-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250619-dtb_fixes-v3-1-9cb02ddd8ce4@bootlin.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMsMarek Vasut
Add bootph-all property to sysinfo EEPROM on Renesas R-Car Gen3 Salvator-X(S), ULCB, Condor, Ebisu, Draak boards. The sysinfo EEPROM is used by U-Boot early on, mark it using the bootph-all property. No functional change for the Linux kernel, this only reduces the divergence of DTs between U-Boot and Linux. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250608215212.1619182-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: renesas: sparrow-hawk: Describe split PCIe clockMarek Vasut
The Sparrow Hawk board supplies the PCIe controller input clock and PCIe bus clock from separate outputs of the Renesas 9FGV0441 clock generator. Describe this split bus configuration in the board DT. The topology looks as follows: ____________ _____________ | R-Car PCIe | | PCIe device | | | | | | PCIe RX<|==================|>PCIe TX | | PCIe TX<|==================|>PCIe RX | | | | | | PCIe CLK<|======.. ..======|>PCIe CLK | '------------' || || '-------------' || || ____________ || || | 9FGV0441 | || || | | || || | CLK DIF0<|======'' || | CLK DIF1<|=========='' | CLK DIF2<| | CLK DIF3<| '------------' Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/20250607194541.79176-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: renesas: r8a779g0: Describe PCIe root portsMarek Vasut
Add nodes which describe the root ports in the PCIe controller DT nodes. This can be used together with the pwrctrl driver to control clock and power supply to a PCIe slot. For example usage, refer to the Sparrow Hawk board. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/20250607194541.79176-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: renesas: ebisu: Add CAN0 supportGeert Uytterhoeven
On R-Car E3, Classical CAN0/1 and CAN-FD share the same sets of pins, so only one of them can be used at the same time. Add support for using CAN0 instead of CAN-FD channel 0 on Ebisu. By default, only CAN-FD channel 0 is enabled, as before. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/612b999870dd64789041e4b0e9c568389b3fb95e.1749048320.git.geert+renesas@glider.be
2025-06-19arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 supportLad Prabhakar
Enable USB2.0 support on the RZ/V2N EVK board, CN2 connector on the EVK supports host/function operation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250528140453.181851-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: renesas: r9a09g056: Add USB2.0 supportLad Prabhakar
The Renesas RZ/V2N (R9A09G056) SoC features a single-channel USB2.0 interface with host and peripheral (function) support. Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0 channel in R9A09G056 SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250528140453.181851-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTSMarek Vasut
Sort DTS alphabetically. Fix up the placement of &rcar_sound {}. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250525160336.82960-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 supportLad Prabhakar
Enable USB2.0 support on the RZ/V2H EVK board, CN3 supports host only operation and CN2 supports host/function operation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250515183104.330964-3-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250613152216.201957-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19arm64: dts: imx8mp-venice-gw74xx: fix TPM SPI frequencyTim Harvey
The IMX8MPDS Table 37 [1] shows that the max SPI master read frequency depends on the pins the interface is muxed behind with ECSPI2 muxed behind ECSPI2 supporting up to 25MHz. Adjust the spi-max-frequency based on these findings. [1] https://www.nxp.com/webapp/Download?colCode=IMX8MPIEC Fixes: 531936b218d8 ("arm64: dts: imx8mp-venice-gw74xx: update to revB PCB") Cc: stable@vger.kernel.org Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19arm64: dts: imx8mp-venice-gw73xx: fix TPM SPI frequencyTim Harvey
The IMX8MPDS Table 37 [1] shows that the max SPI master read frequency depends on the pins the interface is muxed behind with ECSPI2 muxed behind ECSPI2 supporting up to 25MHz. Adjust the spi-max-frequency based on these findings. [1] https://www.nxp.com/webapp/Download?colCode=IMX8MPIEC Fixes: 2b3ab9d81ab4 ("arm64: dts: imx8mp-venice-gw73xx: add TPM device") Cc: stable@vger.kernel.org Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19arm64: dts: imx8mp-venice-gw72xx: fix TPM SPI frequencyTim Harvey
The IMX8MPDS Table 37 [1] shows that the max SPI master read frequency depends on the pins the interface is muxed behind with ECSPI2 muxed behind ECSPI2 supporting up to 25MHz. Adjust the spi-max-frequency based on these findings. [1] https://www.nxp.com/webapp/Download?colCode=IMX8MPIEC Fixes: 5016f22028e4 ("arm64: dts: imx8mp-venice-gw72xx: add TPM device") Cc: stable@vger.kernel.org Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19arm64: dts: imx8mp-venice-gw71xx: fix TPM SPI frequencyTim Harvey
The IMX8MPDS Table 37 [1] shows that the max SPI master read frequency depends on the pins the interface is muxed behind with ECSPI2 muxed behind ECSPI2 supporting up to 25MHz. Adjust the spi-max-frequency based on these findings. [1] https://www.nxp.com/webapp/Download?colCode=IMX8MPIEC Fixes: 1a8f6ff6a291 ("arm64: dts: imx8mp-venice-gw71xx: add TPM device") Cc: stable@vger.kernel.org Signed-off-by: Tim Harvey <tharvey@gateworks.com> Link: https://lore.kernel.org/stable/20250523173723.4167474-1-tharvey%40gateworks.com Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19arm64: dts: add ngpios for vf610 compatible gpio controllersHaibo Chen
After commit da5dd31efd24 ("gpio: vf610: Switch to gpio-mmio"), the vf610 GPIO driver no longer uses the static number 32 for gc->ngpio. This allows users to configure the number of GPIOs per port. And some gpio controllers did have less pads. So add 'ngpios' here, this can save some memory when request bitmap, and also show user more accurate information when use gpio tools. Besides, some gpio controllers have hole in the gpio ranges, so use 'gpio-reserved-ranges' to cover that, then the gpioinfo tool show the correct result. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 08:36:36 +0000