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path: root/arch/arm/boot/dts/aspeed-g5.dtsi
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2017-03-06ARM: dts: aspeed: add SPI controller bindingsCédric Le Goater
Let's define the SPI controllers in the Aspeed SoCs AST2500 and AST2400 and also enable these, as well as the chips, on the associated platforms. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed: Add ftgmac100 to g4 and g5 platformsJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add gpio controller to devicetreeAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add syscon and pin controller nodesAndrew Jeffery
The pin controller's child nodes expose the functions currently implemented in the g5 pin controller driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add LPC Controller nodeAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add SoC Display Controller nodeAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09arm/dst: Add Aspeed ast2500 device treeJoel Stanley
This adds a common device tree for all fifth generation Aspeed systems, and a board specific device tree for the ast2500 evaluation board. Signed-off-by: Joel Stanley <joel@jms.id.au>