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2025-07-16dt-bindings: clock: qcom: document the Milos Display Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Display Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Camera Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Global Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Global Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatibleStephan Gerhold
X1E80100 videocc is largely identical to SM8550, but needs slightly different PLL frequencies. Add a separate qcom,x1e80100-videocc compatible to the existing schema used for SM8550. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-1-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos TCSR Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) TCSR Clock Controller. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-3-b49f19055768@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: Document the Milos RPMH Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) RPMH Clock Controller. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-1-b49f19055768@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Video clock controllerTaniya Das
Add DT bindings for the Video clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controllerTaniya Das
Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Display clock controllerTaniya Das
Add DT bindings for the Display clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Camera clock controllerTaniya Das
Add DT bindings for the Camera clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into ↵Bjorn Andersson
clk-for-6.17 Merge the IPQ5018 CMN PLL binding through a topic branch, to allow merging the clock defines into DeviceTree branch as well.
2025-07-16dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoCGeorge Moussalem
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatibleLuca Weiss
Document the Milos compatible used to describe the pmic glink on this SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-11-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side ↵Luca Weiss
channel Document the Always-On Subsystem side channel on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-7-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: firmware: qcom,scm: document Milos SCM Firmware InterfaceLuca Weiss
Document the SCM Firmware Interface on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-4-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16net/mlx5e: Add device PCIe congestion ethtool statsDragos Tatulea
Implement the PCIe Congestion Event notifier which triggers a work item to query the PCIe Congestion Event object. The result of the congestion state is reflected in the new ethtool stats: * pci_bw_inbound_high: the device has crossed the high threshold for inbound PCIe traffic. * pci_bw_inbound_low: the device has crossed the low threshold for inbound PCIe traffic * pci_bw_outbound_high: the device has crossed the high threshold for outbound PCIe traffic. * pci_bw_outbound_low: the device has crossed the low threshold for outbound PCIe traffic The high and low thresholds are currently configured at 90% and 75%. These are hysteresis thresholds which help to check if the PCI bus on the device side is in a congested state. If low + 1 = high then the device is in a congested state. If low == high then the device is not in a congested state. The counters are also documented. A follow-up patch will make the thresholds configurable. Signed-off-by: Dragos Tatulea <dtatulea@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1752589821-145787-3-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-16s390/net: Remove NETIUCV device driverNagamani PV
The netiucv driver creates TCP/IP interfaces over IUCV between Linux guests on z/VM and other z/VM entities. Rationale for removal: - NETIUCV connections are only supported for compatibility with earlier versions and not to be used for new network setups, since at least Linux kernel 4.0. - No known active users, use cases, or product dependencies - The driver is no longer relevant for z/VM networking; preferred methods include: * Device pass-through (e.g., OSA, RoCE) * z/VM Virtual Switch (VSWITCH) The IUCV mechanism itself remains supported and is actively used via AF_IUCV, hvc_iucv, and smsg_iucv. Signed-off-by: Nagamani PV <nagamani@linux.ibm.com> Reviewed-by: Alexandra Winter <wintera@linux.ibm.com> Signed-off-by: Alexandra Winter <wintera@linux.ibm.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20250715074210.3999296-1-wintera@linux.ibm.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-16dt-bindings: net: cdns,macb: Add external REFCLK propertyRyan Wanner
REFCLK can be provided by an external source so this should be exposed by a DT property. The REFCLK is used for RMII and in some SoCs that use this driver the RGMII 125MHz clk can also be provided by an external source. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/d558467c4d5b27fb3135ffdead800b14cd9c6c0a.1752510727.git.Ryan.Wanner@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-16doc: xdp: Clarify driver implementation for XDP Rx metadataSong Yoong Siang
Clarify that drivers must remove device-reserved metadata from the data_meta area before passing frames to XDP programs. Additionally, expand the explanation of how userspace and BPF programs should coordinate the use of METADATA_SIZE, and add a detailed diagram to illustrate pointer adjustments and metadata layout. Also describe the requirements and constraints enforced by bpf_xdp_adjust_meta(). Signed-off-by: Song Yoong Siang <yoong.siang.song@intel.com> Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org> Acked-by: Stanislav Fomichev <sdf@fomichev.me> Link: https://lore.kernel.org/r/20250716154846.3513575-1-yoong.siang.song@intel.com
2025-07-16dt-bindings: thermal: rockchip: document otp thermal trimNicolas Frattaroli
Several Rockchip SoCs, such as the RK3576, can store calibration trim data for thermal sensors in OTP cells. This capability should be documented. Such a rockchip thermal sensor may reference cell handles that store both a chip-wide trim for all the sensors, as well as cell handles for each individual sensor channel pointing to that specific sensor's trim value. Additionally, the thermal sensor may optionally reference cells which store the base in terms of degrees celsius and decicelsius that the trim is relative to. Each SoC that implements this appears to have a slightly different combination of chip-wide trim, base, base fractional part and per-channel trim, so which ones do which is documented in the bindings. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-4-b6e9efbf1015@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-07-16dt-bindings: rockchip-thermal: Add RK3576 compatibleNicolas Frattaroli
Add a new compatible for the thermal sensor device on the RK3576 SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-2-b6e9efbf1015@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-07-16Documentation: amd-pstate:fix minimum performance state label errorshouyeliu
In the AMD P-States Performance Scale diagram, the labels for "Max Perf" and "Lowest Perf" were incorrectly used to define the range for "Desired Perf".The "Desired performance target" should be bounded by the "Maximum requested performance" and the "Minimum requested performance", which corresponds to "Max Perf" and "Min Perf", respectively. Signed-off-by: Shouye Liu <shouyeliu@tencent.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20250522070140.17557-1-shouyeliu@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
2025-07-16fs: change write_begin/write_end interface to take struct kiocb *Taotao Chen
Change the address_space_operations callbacks write_begin() and write_end() to take struct kiocb * as the first argument instead of struct file *. Update all affected function prototypes, implementations, call sites, and related documentation across VFS, filesystems, and block layer. Part of a series refactoring address_space_operations write_begin and write_end callbacks to use struct kiocb for passing write context and flags. Signed-off-by: Taotao Chen <chentaotao@didiglobal.com> Link: https://lore.kernel.org/20250716093559.217344-4-chentaotao@didiglobal.com Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-07-16dt-bindings: nvmem: convert vf610-ocotp.txt to yaml formatFrank Li
Convert vf610-ocotp.txt to yaml format. Additional changes: - Remove label in examples. - Add include file in examples. - Move reg just after compatible in examples. - Add ref: nvmem.yaml and nvmem-deprecated-cells.yaml - Remove #address-cells and #size-cells from required list to match existed dts file. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-9-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: mediatek: efuse: split MT8186/MT8188 from base versionChen-Yu Tsai
On MT8186 and MT8188 one of the NVMEM cells contains the GPU speed bin value. In combination with the GPU OPP bindings, on these two platforms there is an implied scheme of converting the cell value to what the GPU OPP "opp-supported-hw" property matches. This does not apply to the base mediatek,efuse hardware, nor does it apply to any of the other platforms that do not have the GPU speed bin cell. The platform maintainer argues that this makes the compatibles incompatible with the base "mediatek,efuse" compatible, as shown in the link given. Deprecate the MT8186/MT8188 + "mediatek,efuse" combination, and add new entries with MT8186 being the base model and MT8188 falling back to MT8186. Link: https://lore.kernel.org/all/11028242-afe4-474a-9d76-cd1bd9208987@collabora.com/ Fixes: ff1df1886f43 ("dt-bindings: nvmem: mediatek: efuse: Add support for MT8188") Cc: Johnson Wang <johnson.wang@mediatek.com> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-8-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: SID: Add binding for A523 SID controllerMikhail Kalashnikov
The SID controller should be compatible with A64 and others SoC with 0x200 offset. Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-7-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: convert lpc1857-eeprom.txt to yaml formatFrank Li
Convert lpc1857-eeprom.txt to yaml format. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-5-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: fixed-layout: Allow optional bit positionsSven Peter
NVMEM nodes can optionally include the bits property to specify the bit position of the cell within a byte. Extend patternProperties to allow adding the bit offset to the node address to be able to distinguish nodes with the same address but different bit positions, e.g. trim@54,4 { reg = <0x54 1>; bits = <4 2>; }; trim@54,0 { reg = <0x54 1>; bits = <0 4>; }; Before the conversion to NVMEM layouts in commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") this extension was originally added with commit 4b2545dd19ed ("dt-bindings: nvmem: Extend patternProperties to optionally indicate bit position") to the now deprecated layout. Signed-off-by: Sven Peter <sven@kernel.org> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-3-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16ASoC: dt-bindings: qcom,lpass-va-macro: Define clock-names in top-levelKrzysztof Kozlowski
Device variants use different amount of clock inputs, but all of them are in the same order, 'clock-names' in top-level properties can define the list and each if:then: block can only narrow the number of items. This is preferred syntax, because it keeps list unified among devices and encourages adding new entries to the end of the list, instead of adding them in the middle. The change has no functional impact, but partially reverts approach implemented in commit cfad817095e1 ("ASoC: dt-bindings: qcom,lpass-va-macro: Add missing NPL clock"). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250716074957.102402-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-07-16dt-bindings: display: Add Sitronix ST7567 LCD ControllerJavier Martinez Canillas
Sitronix ST7567 is a monochrome Dot Matrix LCD Controller. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Marcus Folkesson <marcus.folkesson@gmail.com> Link: https://lore.kernel.org/r/20250715110411.448343-5-javierm@redhat.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-07-16ovpn: reject unexpected netlink attributesAntonio Quartulli
Netlink ops do not expect all attributes to be always set, however this condition is not explicitly coded any where, leading the user to believe that all sent attributes are somewhat processed. Fix this behaviour by introducing explicit checks. For CMD_OVPN_PEER_GET and CMD_OVPN_KEY_GET directly open-code the needed condition in the related ops handlers. While for all other ops use attribute subsets in the ovpn.yaml spec file. Fixes: b7a63391aa98 ("ovpn: add basic netlink support") Reported-by: Ralf Lici <ralf@mandelbit.com> Closes: https://github.com/OpenVPN/ovpn-net-next/issues/19 Signed-off-by: Antonio Quartulli <antonio@openvpn.net>
2025-07-16dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920Sowon Na
Add hsi2 compatible for ExynosAutov920 ufs shareability register to set io coherency of the ExynosAutov920 ufs. Signed-off-by: Sowon Na <sowon.na@samsung.com> Link: https://lore.kernel.org/r/20250702013316.2837427-4-sowon.na@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-07-16gpio: sysfs: export the GPIO directory locally in the gpiochip<id> directoryBartosz Golaszewski
As a way to allow the user-space to stop referring to GPIOs by their global numbers, introduce a parallel group of line attributes for exported GPIO that live inside the GPIO chip class device and are referred to by their HW offset within their parent chip. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250704-gpio-sysfs-chip-export-v4-8-9289d8758243@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-16gpio: sysfs: add a parallel class device for each GPIO chip using device IDsBartosz Golaszewski
In order to enable moving away from the global GPIO numberspace-based exporting of lines over sysfs: add a parallel, per-chip entry under /sys/class/gpio/ for every registered GPIO chip, denoted by device ID in the file name and not its base GPIO number. Compared to the existing chip group: it does not contain the "base" attribute as the goal of this change is to not refer to GPIOs by their global number from user-space anymore. It also contains its own, per-chip export/unexport attribute pair which allow to export lines by their hardware offset within the chip. Caveat #1: the new device cannot be a link to (or be linked to by) the existing "gpiochip<BASE>" entry as we cannot create links in /sys/class/xyz/. Caveat #2: the new entry cannot be named "gpiochipX" as it could conflict with devices whose base is statically defined to a low number. Let's go with "chipX" instead. While at it: the chip label is unique so update the untrue statement when extending the docs. Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250704-gpio-sysfs-chip-export-v4-2-9289d8758243@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-16Documentation: driver-api: Update libata error handler informationDamien Le Moal
Update ``->error_handler()`` section of the libata documentation file Documentation/driver-api/libata.rst to remove the reference to the function ata_do_eh() as that function was removed. The reference to the function ata_bmdma_drive_eh() is also removed as that function does not exist at all. And while at it, cleanup the description of the various reset operations using a bullet list. Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Link: https://lore.kernel.org/r/20250716020315.235457-4-dlemoal@kernel.org Signed-off-by: Niklas Cassel <cassel@kernel.org>
2025-07-16Documentation/kernel-parameters: Update rcu_normal_wake_from_gp docUladzislau Rezki (Sony)
Update the documentation about rcu_normal_wake_from_gp parameter. Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Uladzislau Rezki (Sony) <urezki@gmail.com> Reviewed-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Neeraj Upadhyay (AMD) <neeraj.upadhyay@kernel.org>
2025-07-15KVM: arm64: Document registers exposed via KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGSMarc Zyngier
We never documented which GICv3 registers are available for save/restore via the KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS interface. Let's take the opportunity of adding the EL2 registers to document the whole thing in one go. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250714122634.3334816-12-maz@kernel.org [ oliver: fix trailing whitespace ] Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-07-15spi: dt-bindings: spi-mux: Drop "spi-max-frequency" as requiredRob Herring (Arm)
There's little reason to require the SPI mux to define a maximum bus frequency as the muxing is just the chip select and devices still define their maximum freq. In fact, several users don't set "spi-max-frequency" which caused warnings. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://patch.msgid.link/20250715202711.1882103-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-07-15Documentation: ioctl-number: Don't repeat macro namesBagas Sanjaya
Don't repeat mentioning macro names (_IO, _IOW, _IOR, and _IOWR) to keep the wording effective. Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250715024258.16882-3-bagasdotme@gmail.com
2025-07-15Documentation: ioctl-number: Shorten macros tableBagas Sanjaya
The macros table has three columns: the second one is "an" and the third one writes "an ioctl with ... parameters". Simplify the table by adding heading row that indicates macro name and accepted parameters. Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250715024258.16882-2-bagasdotme@gmail.com
2025-07-15Documentation: ioctl-number: Correct full path to papr-physical-attestation.hBagas Sanjaya
Commit 03c9d1a5a30d93 ("Documentation: Fix description format for powerpc RTAS ioctls") fixes Sphinx warning by chopping arch/ path component of papr-physical-attestation.h to fit existing "Include File" column. Now that the column has been widened just enough for that header file, add back its arch/ path component. Reviewed-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Acked-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250714015711.14525-4-bagasdotme@gmail.com
2025-07-15Documentation: ioctl-number: Extend "Include File" column widthBagas Sanjaya
Extend width of "Include File" column to fit full path to papr-physical-attestation.h in later commit. Reviewed-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Acked-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250714015711.14525-3-bagasdotme@gmail.com
2025-07-15Documentation: ioctl-number: Fix linuxppc-dev mailto linkBagas Sanjaya
Spell out full Linux PPC mailing list address like other subsystem mailing lists listed in the table. Reviewed-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Acked-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250714015711.14525-2-bagasdotme@gmail.com
2025-07-15overlayfs.rst: fix typosMatthias Frank
Grammatical fixes Signed-off-by: Matthias Frank <frank.mt125@gmail.com> Acked-by: Amir Goldstein <amir73il@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250710050607.2891-1-frank.mt125@gmail.com
2025-07-15Documentation: core-api: entry: Fix typo "systcalls" -> "syscalls"Andrew Donnellan
Fix a typo: "systcalls" should be "syscalls". Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Nicolas Saenz Julienne <nsaenzju@redhat.com> Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250715061529.56268-1-ajd@linux.ibm.com
2025-07-15Merge tag 'chinese-doc-6.16-rc1' of ↵Jonathan Corbet
gitolite.kernel.org:pub/scm/linux/kernel/git/alexs/linux into docs-mw Chinese translation docs for 6.16-rc1 from Alex Shi This is the Chinese translation subtree for 6.16-rc1. It includes few changes: - Updates to the process documentation - Added translations for network and speculation docs - Polished zh_CN/how-to.rst The above patches have been tested by 'make htmldocs'
2025-07-15dt-bindings: usb: convert lpc32xx-udc.txt to yaml formatFrank Li
Convert lpc32xx-udc.txt to yaml format. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250623203011.2473290-1-Frank.Li@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-15KVM: Documentation: document how KVM is testedPaolo Bonzini
Proper testing greatly simplifies both patch development and review, but it can be unclear what kind of userspace or guest support should accompany new features. Clarify maintainer expectations in terms of testing expectations; additionally, list the cases in which open-source userspace support is pretty much a necessity and its absence can only be mitigated by selftests. While these ideas have long been followed implicitly by KVM contributors and maintainers, formalize them in writing to provide consistent (though not universal) guidelines. Suggested-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-07-15KVM: Documentation: minimal updates to review-checklist.rstPaolo Bonzini
While the file could stand a larger update, these are the bare minimum changes needed to make it more widely applicable. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-07-15dt-bindings: display: panel: samsung,atna30dw01: document ATNA30DW01Dale Whinham
The Samsung ATNA30DW01 panel is a 13" AMOLED eDP panel. It is similar to the ATNA33XC20 except that it is smaller and has a higher resolution. Tested-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Signed-off-by: Dale Whinham <daleyo@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250714173554.14223-3-daleyo@gmail.com
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 01:11:02 +0000