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2019-05-24drm/amdgpu: Add new PSP cmd GFX_CMD_ID_PROG_REGTrigger Huang
Add new PSP command GFX_CMD_ID_PROG_REG definition Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: initialize PSP before IH under SR-IOVTrigger Huang
In order to support new PSP feature that PSP may provide interface to program IH CNTL register, initialize PSP before IH under Vega10 SR-IOV VF Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: init vega10 SR-IOV reg access modeTrigger Huang
Set different register access mode according to the features provided by firmware Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: gpu reset will run ras post initxinhui pan
ras need initialize proper state after late init Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: sdma support ras gpu resetxinhui pan
request a gpu reset if ras return EAGAIN. we will run late init again so it is ok to do nothing this time. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: gfx support ras gpu resetxinhui pan
request a gpu reset if ras return EAGAIN. we will run late init again so it is ok to do nothing this time. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: gmc support ras gpu resetxinhui pan
request a gpu reset if ras return EAGAIN. we will run late init again so it is ok to do nothing this time. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: handle ras resetxinhui pan
add another flag to allow IP do a gpu reset after device init. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Issue ras TA disable/enable cmd forcely on bootxinhui pan
Check ras TA error code and return EAGAIN. Issue ras enable/disable cmd without checking currect state. Looks like ras TA will handle current state == target state case. Now driver might need do a reset to satisfy ras TA. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Revert "drm/amdgpu: skip gpu reset when ras error occured"xinhui pan
Enable this now to reset the GPU on RAS errors. This reverts commit 138352e5752aa3e694951d70c8fe8730219f4edf. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: gpu reset will run late_initxinhui pan
ras need late init to initialize proper state. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: add df perfmon regs and funcs for xgmiJonathan Kim
v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabledJames Zhu
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: add EDC counter registerJames Zhu
Add EDC counter register to support gfx9 gpr EDC workaround to clear all EDC counters. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Reserve shared fence for eviction fenceFelix Kuehling
Need to reserve space for the shared eviction fence when initializing a KFD VM. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Expose send immediate sdp message interfaceLeo (Hanghong) Ma
[Why] To send sdp message immediately from a single slot. [How] Modify the generic SDP message interface, and use GSP4 to send immediate sdp message. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Fill plane attrs only for valid pxl formatRoman Li
[Why] In fill_plane_buffer_attributes() we calculate chroma/luma assuming that the surface_pixel_format is always valid. If it's not the case, there's a risk of divide by zero error. [How] Check if format valid before calculating pixel format attributes Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: move back vbios cmd table for set dprefclkEric Yang
[Why] Upon closer inspection, our previous implementation is missing code for programming de-spread and DP DTO. Porting this logic into driver is rather involved, as there are a lot of table look ups. So for now move back to calling vbios cmd table [How] Go back to calling vbios cmd table for set dp_refclk Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: fix acquire_first_split_pipe functionDmytro Laktyushkin
This function needs to re-calculate the scaling on the pipe that loses it's half. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: stop external access to internal optc sync paramsDmytro Laktyushkin
These are internal otg params and should be handled as such. Thich change passes the params as function arguments. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: move signal type out of otg dlg paramsDmytro Laktyushkin
It makes no logical sense being there Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: reset retimer/redriver below 340MhzCharlene Liu
[Description] This is for HDMI 6Ghz mode before we load the driver, because VBIOS not support HDMI (6Ghz mode) Reset to redriver/retimer setting for the setting for below 340Mhz. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: color space ycbcr709 supportCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Duke Du <Duke.Du@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Define Byte 14 on AVI InfoFrameChris Park
[Why] Part of HDMI 2.1 requires AVI InfoFrame version update from current V2 to V4 for new colorimetry. [How] Define V4 AVI InfoFrame ACE0-ACE3 bit. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: 3.2.29Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Disable cursor when offscreen in negative directionNicholas Kazlauskas
[Why] When x or y is negative we set the x and y values to 0 and compensate with a positive cursor hotspot in DM since DC expects positive cursor values. When x or y is less than or equal to the maximum cursor width or height the cursor hotspot is clamped so the hotspot doesn't exceed the cursor size: if (x < 0) { xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); x = 0; } if (y < 0) { yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); y = 0; } This incorrectly forces the cursor to be at least 1 pixel on the screen in either direction when x or y is sufficiently negative. [How] Just disable the cursor when it goes far enough off the screen in one of these directions. This fixes kms_cursor_crc@cursor-256x256-offscreen. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Fill prescale_params->scale for RGB565Nicholas Kazlauskas
[Why] An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565 formats on DCE since the prescale_params->scale wasn't being filled. Found by a dmesg-fail when running the igt@kms_plane@pixel-format-pipe-a-planes test on Baffin. [How] Fill in the scale parameter. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Support AVI InfoFrame V3 and V4Chris Park
[Why] Part of HDMI 2.1 requires AVI InfoFrame version update from current V2 to V3 for new VICs, and V4 for new colorimetry. [How] Implement V3 and V4 AVI InfoFrame. If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), the Source shall use 20 AVI InfoFrame Version 4. If VIC >= 128, the Source shall use AVI InfoFrame Version 3 Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: block passive dongle EDID Emulation for USB-C portsSamson Tam
[Why] Emulating passive dongle on USB-C port causes issue on some asics. [How] Check for DP_IS_USB_C flag in bios parser and propagate it to encoder features flags. If DP_IS_USB_C flag is set and it is trying to emulate passive dongle, then return fail. Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: add SW_USE_I2C_REG request.Charlene Liu
[Description] This is for DC_I2c arbitration use between HW use/SW use and DMCU use. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: add support for disconnected eDP panelsJun Lei
[why] On some configurations, eDP from GPU is muxed with another GPU. DC does not know state of mux, but DM has this knowledge. This flag allows DC to ignore creating EDP link when DM informs DC that EDP mux is not connected. [how] Add flag to dc, populate flag in DM Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Set dispclk and dprefclock directlyEric Yang
[Why] To simply logic for setting DCN specific clocks, we will send SMU message directly through the VBIOS message box. [How] Add new structure in pp_smu to hold functions to set clocks through vbios message box Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: fix multi display seamless boot caseAnthony Koo
[Why] There is a scenario that causes eDP to become blank if there are multiple displays connected, and the external display is set as the primary display such that the first flip comes to the external display. In this scenario, we call our optimize function before the eDP even has a chance to flip. [How] There is a check that prevents bandwidth optimize from occurring before first flip is complete on the seamless boot display. But actually it assumed the seamless boot display is the first one to flip. But in this scenario it is not. Modify the check to ensure the steam with the seamless boot flag set is the one that has completed the first flip. Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: Refactor program watermark.Yongqiang Sun
Refactor programming watermark function: Divided into urgent watermark, stutter watermark and pstate watermark. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/display: 3.2.28Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: rename amdgpu_prime.[ch] into amdgpu_dma_buf.[ch]Christian König
We are getting a dma-buf implementation completely separate from drm prime, so rename the files now and cleanup the code a bit. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/amdgpu: Add MEM_LOAD to amdgpu_pm_info debugfs fileTom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdkfd: Cosmetic cleanupKent Russell
Fix some spacing issues, log output, uses of !=NULL/==NULL, unneeded extra lines and clean up a declaration from =1 to =true for clarity Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Fix CIK references in gmc_v8Kent Russell
gmc_v8 is for VI, not CIK, so fix those references Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Add PCIe replay count sysfs fileKent Russell
Add a sysfs file for reporting the number of PCIe replays (NAKs). This returns the sum of NAKs received and NAKs generated Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Add replay counter defines to NBIO headersKent Russell
Add the PCIE_RX_NUM_NACK and PCIE_RX_NUM_NACK_GENERATED values to the NBIO SMN headers in preparation for exposing the number of PCIe replays via sysfs Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Update latest xgmi topology info after each device is enumulatedshaoyunl
Adjust the sequence of set/get xgmi topology, so driver can have the latest XGMI topology info for future usage Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: enable separate timeout setting for every ring type V4Evan Quan
Every ring type can have its own timeout setting. - V2: update lockup_timeout parameter format and cosmetic fixes - V3: invalidate 0 and negative values - V4: update lockup_timeout parameter format Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: add new sysfs interface for memory realtime utilizationEvan Quan
A new sysfs interface mem_busy_percent is added for telling how busy the VRAM is(in percentage). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/powerplay: expose SMU7 asics realtime memory utilizationEvan Quan
Enable realtime memory utilization report on SMU7 asics. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/powerplay: expose Vega12 realtime memory utilizationEvan Quan
Enable realtime memory utilization report on Vega12. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amd/powerplay: expose Vega20 realtime memory utilizationEvan Quan
Enable realtime memory utilization report on Vega20. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdkfd: Adjust weight to represent num_hops info when report xgmi iolinkshaoyunl
Upper level runtime need the xgmi hops info to determine the data path Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Implement get num of hops between two xgmi deviceshaoyunl
KFD need to provide the info for upper level to determine the data path Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdkfd: Expose HDP registers to user spaceOak Zeng
Introduce a new memory type (KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) and expose mmio page of HDP registers to user space through this new memory type. v2: moved remapped hdp regs to adev struct v3: rename the new memory type to ALLOC_MEM_FLAGS_MMIO_REMAP v4: use more generic function name v5: Fail remapped mmio allocation for asics before gfx9 Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-31 04:14:50 +0000