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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Cleanup of ARM64 DTS for v5.20, part two
Remaining cleanups for ARM64 DTS: gpio-keys and led node names on Marvel
platforms.
* tag 'dt64-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: marvell: armada-3720: align lednode names with dtschema
arm64: dts: marvell: align gpio-key node names with dtschema
Link: https://lore.kernel.org/r/20220706163754.33064-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
Armv8 Juno/FVP updates for v5.20
Just a small bunch of miscellaneous updates: addition of missing
cache-level property to L2 caches on Juno, whitespace adjustments
and removal of erroneous 'mbox-name' and 'panel-dpi' compatible in
the device tree nodes.
* tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add cache-level property to L2 caches
arm64: dts: arm: adjust whitespace around '='
arm64: dts: arm/juno: Drop erroneous 'mbox-name' property
arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatible
Link: https://lore.kernel.org/r/20220706115026.2272643-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.20, round 1
Highlights:
----------
- MCU:
-Fix whitespace coding style. No functional changes.
- MPU:
- General:
- Remove specific IPCC wakeup interrupt on STM32MP15.
- Enable OPTEE firmware and scmi support (clock/reset) on
STM32MP13. It allows to enable RCC clock driver.
- Add new pins configurations groups.
- DH boards:
- Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN,
uSD, USB, eMMC and SDIO wifi.
- Add ST MIPID02 bindings to AV96 (not enabled by default)
- OSD32:
- Correct vcc-supply for eeprom.
- fix missing internally connected voltage regulator (ldo3
supplied by vdd_ddr).
* tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits)
ARM: dts: stm32: Add ST MIPID02 bindings to AV96
ARM: dts: stm32: Add alternate pinmux for RCC pin
ARM: dts: stm32: Add alternate pinmux for DCMI pins
ARM: dts: stm32: Add DHCOR based DRC Compact board
ARM: dts: stm32: Add alternate pinmux for UART5 pins
ARM: dts: stm32: Add alternate pinmux for UART4 pins
ARM: dts: stm32: Add alternate pinmux for UART3 pins
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
ARM: dts: stm32: Add alternate pinmux for CAN1 pins
dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact
ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15
ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk
ARM: dts: stm32: add RCC on STM32MP13x SoC family
ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
dt-bindings: rcc: stm32: select the "secure" path for stm32mp13
ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32
ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1
ARM: dts: stm32: adjust whitespace around '=' on MCU boards
ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151
...
Link: https://lore.kernel.org/r/a250f32b-f67c-2922-0748-e39dc791e95c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT for v5.20
It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
with reality
* tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: lan966x: Add UDPHS support
dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string
ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.
ARM: dts: lan966x: Add mcan1 node.
ARM: dts: at91: sama7g5: add reset-controller node
ARM: dts: at91: use generic name for reset controller
ARM: dts: at91: sama5d2: fix compilation warning
ARM: dts: at91: sama5d2: fix compilation warning
Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt
Ux500 DTS updates for the v5.20 kernel:
- Fix orientation matrices on a few U8500 mobile phones.
- Drop unused i2c power supply handled by the power domain.
* tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ux500: Drop unused i2c power domain supply
ARM: dts: ux500: Fix Gavini accelerometer mounting matrix
ARM: dts: ux500: Fix Codina accelerometer mounting matrix
ARM: dts: ux500: Fix Janice accelerometer mounting matrix
Link: https://lore.kernel.org/r/CACRpkdY1MG=HG+tOCmD1_LEAStV1-ycCLkwShMRD4R=4jGDYHQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
NFC flash node on rk3066a-mk808 and some dts styling fixes
(alignment and node names).
* tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: correct gpio-keys properties on rk3288-tinker
ARM: dts: rockchip: align gpio-key node names with dtschema
ARM: dts: rockchip: adjust whitespace around '='
ARM: dts: rockchip: enable nfc node in rk3066a-mk808.dts
Link: https://lore.kernel.org/r/14795241.VsHLxoZxqI@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New board the Radxa Rock Pi S, enablement of graphics support and hdmi-audio
on rk356x in general plus necessary board-specific changes on Rock-3A,
Quartz64-A, rk3568-evb, BPI-R2-Pro.
A number of additional peripherals on BPI-R2-Pro (gpu, thermal, rtc) and
PCIe2x1 support on rk3568 and enablement on Quart64-A as well as a number
of additional peripherals to this board (sfc node, sdr-104 support, fan).
And finally touch panel support for rockpro64 and some misc dt cleanups
(node names for dtschema and styling).
* tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits)
arm64: dts: rockchip: enable hdmi tx audio on rock-3a
arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10
arm64: dts: rockchip: align gpio-key node names with dtschema
arm64: dts: rockchip: rock-pi-s add more peripherals
arm64: dts: rockchip: add ROCK Pi S DTS support
dt-bindings: arm: rockchip: Add Radxa ROCK Pi S
arm64: dts: rockchip: Add missing space around regulator-name on rk3368-orion-r68
arm64: dts: rockchip: enable the gpu on BPI-R2-Pro
arm64: dts: rockchip: configure thermal shutdown for BPI-R2-Pro
arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro
arm64: dts: rockchip: enable vop2 and hdmi tx on BPI-R2-Pro
arm64: dts: rockchip: set display regulators to always-on on BPI-R2-Pro
arm64: dts: rockchip: add RTC to BPI-R2 Pro
arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
arm64: dts: rockchip: Add HDMI audio nodes to rk356x
arm64: dts: rockchip: adjust whitespace around '='
arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a
arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
arm64: dts: rockchip: rk356x: Add HDMI nodes
...
Link: https://lore.kernel.org/r/40088956.J2Yia2DhmK@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT.
Both the ST MIPID02 and DCMI are disabled by default, as the
AV96 camera module is optional.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for RCC pin, this is used on AV96 board
for e.g. sensor clock supply.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for DCMI pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for UART5 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for UART4 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for UART3 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for SPI2 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add another mux option for CAN1 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Compact
Add DT compatible string for DH electronics STM32MP15xx DHCOR on DRC Compact
carrier board into YAML DT binding document. This system is a general purpose
DIN Rail Controller design.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add UDPHS (the USB High Speed Device Port controller) support.
The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS
IP. This IP is also the same as the one present in the SAMA5D3
SOC.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-4-herve.codina@bootlin.com
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The USB device controller available in the Microchip LAN9662 SOC
is the same IP as the one present in the SAMA5D3 SOC.
Add the LAN9662 compatible string and set the SAMA5D3 compatible
string as a fallback for the LAN9662.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-3-herve.codina@bootlin.com
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Add the static OP-TEE reserved memory regions.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enables Reset and Clocks Controller on STM32MP13
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable optee and SCMI clocks support.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Like for stm32mp15, when stm32 RCC node is used to interact with a secure
context (using clock SCMI protocol), a different path has to be used for
yaml verification.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
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According to the OSD32MP1 Power System overview[1] the EEPROM is connected to
the VDD line and not to some single-purpose fixed regulator.
Set the EEPROM supply according to the diagram to eliminate this parent-less
regulator.
[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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According to the OSD32MP1 Power System overview[1] ldo3's input is always
internally connected to vdd_ddr.
[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.
The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so
remove the unsupported "wakeup" one.
Note that the EXTI interrupt 61 has two roles : it is hierarchically linked
to the GIC IPCC "rx" interrupt, and it acts as a wakeup source.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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On pcb8291, Flexcom3 usart has only tx and rx pins.
Cleaningup usart3 pinctrl settings.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704135809.6952-1-kavyasree.kotagiri@microchip.com
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This regulator supply is replaced by the proper power
domain.
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220701225339.814962-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Enable the I2S0 controller and the hdmi-sound node on the Radxa
ROCK3 Model A.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20220614230354.3756364-2-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enable the I2S0 controller and the hdmi-sound node on the Rockchip
RK3568 EVB1.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20220614230354.3756364-1-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Devicetree changes omaps for v5.20 merge window
Just one devicetree change to add EEPROM regulator for BeagleBone Black.
* tag 'omap-for-v5.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am33xx: Map baseboard EEPROM on BeagleBone Black
Link: https://lore.kernel.org/r/pull-1656918942-515224@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The USBH composed of EHCI and OHCI controllers needs the PHY clock to be
initialized first, before enabling (gating) them. The reverse is also
required when going to suspend.
So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL
gets enabled 1st upon controller init. Upon suspend/resume, this also makes
the clock to be disabled/re-enabled in the correct order.
This fixes some IRQ storm conditions seen when going to low-power, due to
PHY PLL being disabled before all clocks are cleanly gated.
Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c")
Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Delete the node fixed clock managed by secure world with SCMI.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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LSE clock is provided by SCMI.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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The peripheral clock of CEC is not LSE but CEC.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
regulators through SCMI service. This is needed since enabling secure
only access to RCC clock and reset controllers also enables secure
access only on PWR voltage regulators reg11, reg18 and usb33 hence
these must also be accessed through SCMI Voltage Domain protocol.
This change applies on commit [2] that already corrects issues from
commit [1].
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add the mcan1 node. By default, keep it disabled.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220627110552.26315-1-kavyasree.kotagiri@microchip.com
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Add reset controller node.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220610092414.1816571-10-claudiu.beznea@microchip.com
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Use generic name for reset controller of AT91 devices to comply with
DT specifications.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
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Fix the following compilation warning:
arch/arm/boot/dts/sama5d2.dtsi:371.29-382.6: Warning
(avoid_unnecessary_addr_size): /ahb/apb/ethernet@f8008000:
unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
also defined at arch/arm/boot/dts/at91-sama5d2_icp.dts:353.8-363.3
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220615080633.1881196-2-claudiu.beznea@microchip.com
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Fix the following compilation warning:
Warning (simple_bus_reg): /ahb/apb/resistive-touch: missing or empty reg/ranges property
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220615080633.1881196-1-claudiu.beznea@microchip.com
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git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/dt
Amlogic ARM64 DT changes for v5.20:
- adjust whitespace around '='
- add reset controller node for Meson-S4 SoC
- correct gpio-keys properties
- align gpio-key node names with dtschema
- add gpio-fan control to GS-King-X
* tag 'amlogic-arm64-dt-for-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
arm64: dts: meson: add gpio-fan control to GS-King-X
arm64: dts: amlogic: align gpio-key node names with dtschema
arm64: dts: amlogic: correct gpio-keys properties
arm64: dts: meson: add reset controller for Meson-S4 SoC
arm64: dts: amlogic: adjust whitespace around '='
Link: https://lore.kernel.org/r/9c8b8570-f20c-ce9a-8c6c-51fdadf7722c@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/dt
Amlogic ARM DT changes for v5.20:
- adjust whitespace around '=' in ARM meson DT
* tag 'amlogic-arm-dt-for-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
ARM: dts: meson: adjust whitespace around '='
Link: https://lore.kernel.org/r/51034acd-13db-5c25-7b9f-ff87537406bd@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Cleanup of ARM DTS for v5.20
Series of cleanups for ARM DTS:
1. White-spaces, gpio-key subnode names, USB DWC3/EHCI node names,
2. Add board-level compatibles to Aspeed evaluation boards.
* tag 'dt-cleanup-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: stih407-family: Harmonize DWC USB3 DT nodes name
ARM: dts: lpc18xx: Harmonize EHCI/OHCI DT nodes name
ARM: dts: ast2600-evb-a1: fix board compatible
ARM: dts: ast2600-evb: fix board compatible
ARM: dts: ast2500-evb: fix board compatible
ARM: dts: animeo: correct gpio-keys properties
ARM: dts: animeo: align gpio-key node names with dtschema
ARM: dts: sd: adjust whitespace around '='
ARM: dts: sti: adjust whitespace around '='
ARM: dts: ste: adjust whitespace around '='
ARM: dts: nuvoton: adjust whitespace around '='
ARM: dts: lpc: adjust whitespace around '='
ARM: dts: ecx: adjust whitespace around '='
ARM: dts: alpine: adjust whitespace around '='
ARM: dts: spear: adjust whitespace around '='
ARM: dts: axm: adjust whitespace around '='
ARM: dts: at91: adjust whitespace around '='
ARM: dts: aspeed: adjust whitespace around '='
ARM: dts: pxa: adjust whitespace around '='
Link: https://lore.kernel.org/r/20220627082842.50508-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Cleanup of ARM64 DTS for v5.20
Series of cleanups for ARM64 DTS: White-spaces, gpio-key subnode names,
USB DWC3/EHCI node names.
* tag 'dt64-cleanup-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: apm: Harmonize DWC USB3 DT nodes name
arm64: dts: hisilicon: correct gpio-keys properties
arm64: dts: hisilicon: align gpio-key node names with dtschema
arm64: dts: broadcom: align gpio-key node names with dtschema
arm64: dts: apm: correct gpio-keys properties
arm64: dts: microchip: adjust whitespace around '='
arm64: dts: sprd: adjust whitespace around '='
arm64: dts: hisilicon: adjust whitespace around '='
arm64: dts: marvell: adjust whitespace around '='
arm64: dts: lg: adjust whitespace around '='
arm64: dts: apm: adjust whitespace around '='
arm64: dts: amd: adjust whitespace around '='
Link: https://lore.kernel.org/r/20220627082842.50508-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA dts updates for v5.20
- Clean up the Mercury++ AA1 dts
- Add support the Google Chameleon v3 board
- Add defined GIC interrupt type for Agilex ECC
- Fix coding style around Stratix10 QSPI dts entry
- Add support for Stratix10 SW Virtual platform
- Move clocks entry out of the Stratix10 soc node
* tag 'socfpga_dts_updates_for_v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
arm64: dts: Add support for Stratix 10 Software Virtual Platform
dt-bindings: altera: document Stratix 10 SWVP compatibles
arm64: dts: altera: adjust whitespace around '='
arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
dt-bindings: altera: Add Chameleon v3 board
ARM: dts: socfpga: Add Google Chameleon v3 devicetree
ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi
Link: https://lore.kernel.org/r/20220626004437.1224820-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.20
- Reorganize the renesas,prr DT binding document.
* tag 'renesas-dt-bindings-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: Move renesas,prr from arm to soc
Link: https://lore.kernel.org/r/cover.1656069640.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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