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2019-09-03ice: Only disable VLAN pruning for the VF when all VLANs are removedBrett Creeley
Currently if the VF adds a VLAN, VLAN pruning will be enabled for that VSI. Also, when a VLAN gets deleted it will disable VLAN pruning even if other VLAN(s) exists for the VF. Fix this by only disabling VLAN pruning on the VF VSI when removing the last VF (i.e. vf->num_vlan == 0). Signed-off-by: Brett Creeley <brett.creeley@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Remove enable DCB when SW LLDP is activatedMichal Swiatkowski
Remove code that enables DCB in initialization when SW LLDP is activated. DCB flag is set or reset before in ice_init_pf_dcb based on number of TCs. So there is not need to overwrite it. Setting DCB without checking number of TCs can cause communication problems with other cards. Host card sends packet with VLAN priority tag, but client card doesn't strip this tag and ping doesn't work. Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Report stats when VSI is downDave Ertman
There is currently a check in get_ndo_stats that returns before updating stats if the VSI is down or there are no Tx or Rx queues. This causes the netdev to report zero stats with the netdev is down. Remove the check so that the behavior of reporting stats is the same as it was in IXGBE. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Always notify FW of VF resetMitch Williams
The call to ice_dis_vsi_txq() acts as the notification to the firmware that the VF is being reset. Because of this, we need to make this call every time we reset, regardless of whatever else we do to stop the Tx queues. Without this change, VF resets would fail to complete on interfaces that were up and running. Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Correctly handle return values for init DCBDave Ertman
In the init path for DCB, the call to ice_init_dcb() can return a non-zero value for either an actual error, or due to the FW lldp engine being stopped. We are currently treating all non-zero values only as an indication that the FW LLDP engine is stopped. Check for an actual error in the DCB init flow. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Limit Max TCs on devices with more than 4 portsUsha Ketineni
This patch limits the max TCs set by the driver to the value provided by the firmware as per the capabilities of the device. Otherwise, hard coding to 8 TC max would fail the device configurations with more than 4 ports. Signed-off-by: Usha Ketineni <usha.k.ketineni@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Cleanup defines in ice_type.hTony Nguyen
Conventionally, if the #defines/other are not needed by other header files being included, #includes are done first followed by #defines and other stuff. Move the #defines before the #includes to follow this convention. Suggested by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: print extra message if topology issueJesse Brandeburg
The driver needs to inform the user if there is an issue with the topology / configuration of the link. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: add print of autoneg state to link messageJesse Brandeburg
Print the state of auto-negotiation when printing the Link up message. Adds new text to the "NIC Link is up" line like Autoneg: <True | False> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: update driver unloading field for Queue Shutdown AQ commandBruce Allan
According to recent specification versions, the field in the Queue Shutdown AdminQ command consisting of the "driver unloading" indication is not a 4 byte field (it is byte.bit 16.0). Change it to a byte and remove the unnecessary endian conversion. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: add needed PFR during driver unloadBruce Allan
According to the specification, a PF Reset must be done as part of the driver unload flow. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Deduce TSA value from the priority value in the CEE modeChinh T Cao
In CEE mode, the TSA information can be derived from the reported priority value. Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Report what the user set for coalesce [tx|rx]-usecsBrett Creeley
Currently if the user sets an odd value for [tx|rx]-usecs we align the value because the hardware only understands ITR values in multiples of 2. This seems misleading because we are essentially telling the user that the ITR value is odd, when in fact we have changed it internally. Fix this by reporting that setting odd ITR values is not allowed. Also, while making changes to ice_set_rc_coalesce() I noticed a bit of code/error duplication. Make the necessary changes to remove the duplication. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Fix resource leak in ice_remove_rule_internal()Jeb Cramer
We don't free s_rule if ice_aq_sw_rules() returns a non-zero status. If it returned a zero status, s_rule would be freed right after, so this implies it should be freed within the scope of the function regardless. Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03ice: Fix EMP reset handlingAnirudh Venkataramanan
ice_reset_subtask needs to handle EMP resets as well, as EMP resets can be triggered by the firmware. This patch adds the logic to do this. Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-09-03net/mlx5: Add devlink flow_steering_mode parameterMaor Gottlieb
Add new parameter (flow_steering_mode) to control the flow steering mode of the driver. Two modes are supported: 1. DMFS - Device managed flow steering 2. SMFS - Software/Driver managed flow steering. In the DMFS mode, the HW steering entities are created through the FW. In the SMFS mode this entities are created though the driver directly. The driver will use the devlink steering mode only if the steering domain supports it, for now SMFS will manages only the switchdev eswitch steering domain. User command examples: - Set SMFS flow steering mode:: $ devlink dev param set pci/0000:06:00.0 name flow_steering_mode value "smfs" cmode runtime - Read device flow steering mode:: $ devlink dev param show pci/0000:06:00.0 name flow_steering_mode pci/0000:06:00.0: name flow_steering_mode type driver-specific values: cmode runtime value smfs Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add support to use SMFS in switchdev modeMaor Gottlieb
In case that flow steering mode of the driver is SMFS (Software Managed Flow Steering), then use the DR (SW steering) API to create the steering objects. In addition, add a call to the set peer namespace when switchdev gets devcom pair event. It is required to support VF LAG in SMFS. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add API to set the namespace steering modeMaor Gottlieb
Add API to set the flow steering root namesapce mode. Setting new mode should be called before any steering operation is executed on the namespace. This API is going to be used by steering users such switchdev. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add direct rule fs_cmd implementationMaor Gottlieb
Add support to create flow steering objects via direct rule API (SW steering). New layer is added - fs_dr, this layer translates the command that fs_core sends to the FW into direct rule API. In case that direct rule is not supported in some feature then -EOPNOTSUPP is returned. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add CONFIG_MLX5_SW_STEERING for software steering supportAlex Vesker
Add new mlx5 Kconfig flag to allow selecting software steering support and compile all the steering files only if the flag is selected. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose APIs for direct rule managingAlex Vesker
Expose APIs for direct rule managing to increase insertion rate by bypassing the firmware. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add required FW steering functionalityAlex Vesker
SW steering is capable of doing many steering functionalities but there are still some functionalities which are not exposed to upper layers and therefore performed by the FW. This is the support for recalculating checksum using a hairpin QP. The recalculation is required after a modify TTL action which skips the needed CS calculation in HW. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering rule functionalityAlex Vesker
Rules are the actual objects that tie matchers, header values and actions. Each rule belongs to a matcher, which can hold multiple rules sharing the same mask. Each rule is a specific set of values and actions. When a packet reaches a matcher it is being matched against the matcher`s rules. In case of a match over a rule its actions will be executed. Each rule object contains a set of STEs, where each STE is a definition of match values and actions defined by the rule. This file handles the rule operations and processing. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering action functionalityAlex Vesker
On rule creation a set of actions can be provided, the actions describe what to do with the packet in case of a match. It is possible to provide a set of actions which will be done by order. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering matcher functionalityAlex Vesker
Matcher defines which packets fields are matched when a packet arrives. Matcher is a part of a table and can contain one or more rules. Where rule defines specific values of the matcher's mask definition. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering table functionalityAlex Vesker
Tables are objects which are used for storing matchers, each table belongs to a domain and defined by the domain type. When a packet reaches the table it is being processed by each of its matchers until a successful match. Tables can hold multiple matchers ordered by matcher priority. Each table has a level. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering domain functionalityAlex Vesker
Domain is the frame for all of the dr (direct rule) objects. There are different domain types which also affect the object under that domain. Each domain can hold multiple tables which can hold multiple matchers and so on, this means that all of the dr (direct rule) objects exist under a specific domain. The domain object also holds the resources needed for other objects such as memory management and communication with the device. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add Steering entry (STE) utilitiesAlex Vesker
Steering Entry (STE) object is the basic building block of the steering map. There are several types of STEs. Each rule can be constructed of multiple STEs. Each STE dictates which fields of the packet's header are being matched as well as the information about the next step in map (hit and miss pointers). The hardware gets a packet and tries to match it against the STEs, going to either the hit pointer or the miss pointer. This file handles the STE operations. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose an internal API to issue RDMA operationsAlex Vesker
Inserting or deleting a rule is done by RDMA read/write operation to SW ICM device memory. This file provides the support for executing these operations. It includes allocating the needed resources and providing an API for writing steering entries to the memory. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Mark Bloch <markb@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, ICM pool memory allocatorAlex Vesker
ICM device memory is used for writing steering rules (STEs) to the NIC. An ICM memory pool allocator was implemented to manage the required memory. The pool consists of buckets, a bucket per chunk size. Once a bucket is empty we will cut a row of memory from the latest allocated MR, if the MR size is not sufficient we will allocate a new MR. HW design requires that chunks memory address should be aligned to the chunk size, this is the reason for managing the MR with row size that insures memory alignment. Current design is greedy in memory but provides quick allocation times in steady state. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add direct rule command utilitiesAlex Vesker
Add direct rule command utilities which consists of all the FW commands that are executed to provide the SW steering functionality. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add the internal direct rule types definitionsAlex Vesker
Add the internal header file that contains various types definition that will be used in coming patches as well as the internal functions decelerations. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add flow steering actions to fs_cmd shim layerMaor Gottlieb
Add flow steering actions: modify header and packet reformat to the fs_cmd shim layer. This allows each namespace to define possibly different functionality for alloc/dealloc action commands. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03can: dev: can_dev_init(): convert from printk(KERN_INFO) to pr_infoMarc Kleine-Budde
This patch converts the printk(KERN_INFO) in can_dev_init() to pr_info(). Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: dev: can_dellink(): remove return at end of void functionMarc Kleine-Budde
This patch remove the return at the end of the void function can_dellink(). Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: dev: can_restart(): convert NULL pointer checkMarc Kleine-Budde
This patch converts the NULL pointer check in can_restart() form "skb == NULL" to "!skb". Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: dev: remove unnecessary blank lineMarc Kleine-Budde
This patch removes unnecessary blank lines, so that checkpatch doesn't complain anymore. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: dev: remove unnecessary parenthesesMarc Kleine-Budde
This patch removes unnecessary parentheses from the generic CAN device infrastructure. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: dev: avoid long linesMarc Kleine-Budde
This patch fixes long lines in the generic CAN device infrastructure. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: dev: convert block comments to network style commentsMarc Kleine-Budde
This patch converts all block comments to network subsystem style block comments. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: mcp251x: Call wrapper instead of regulator_disable()Andy Shevchenko
There is no need to check for regulator presence in the ->suspend() since a wrapper does it for us. Due to this we may unconditionally set AFTER_SUSPEND_POWER flag. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: mcp251x: Make use of device property APIAndy Shevchenko
Make use of device property API in this driver so that both OF based system and ACPI based system can use this driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: mcp251x: Use devm_clk_get_optional() to get the input clockAndy Shevchenko
Simplify the code which fetches the input clock by using devm_clk_get_optional(). This comes with a small functional change: previously all errors were ignored when platform data is present. Now all errors are treated as errors. If no input clock is present devm_clk_get_optional() will return NULL instead of an error which matches the behavior of the old code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: mcp251x: remove deprecated board file setup exampleMarc Kleine-Budde
In the pre device-tree ARM aera there were board files that configured the system (instead of a device tree). A "struct spi_board_info" was used to describe the SPI bus. As new systems should be described via device trees, this patch removes the board setup example from the driver. The "struct mcp251x_platform_data" cannot be removed completely, as there are still some in-tree users of this file. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: tcan4x5x: Remove checking the wake pinDan Murphy
Remove checking the wake pin for every read/write call. The device is not explicitly put to sleep in the code and the POR interrupt is cleared during the init of the device. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: tcan4x5x: Remove data-ready gpio interruptDan Murphy
Remove the data-ready gpio interrupt handling and use the spi->irq that is created based on the interrupt DT property. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03dt-bindings: can: tcan4x5x: Update binding to use interrupt propertyDan Murphy
Remove the data-ready-gpio property in favor of the DT standard interrupt-parent and interrupts. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-03can: kvaser_pciefd: the PWM generator is running at the bus frequency of the ↵Christer Beskow
system. The system clock frequency for the bus connected to the PCIe controller shall be used when calculating the frequency of the PWM, not the CAN system clock frequency. Signed-off-by: Christer Beskow <chbe@kvaser.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-09-02Merge branch 'mvpp2-per-cpu-buffers'David S. Miller
Matteo Croce says: ==================== mvpp2: per-cpu buffers This patchset workarounds an PP2 HW limitation which prevents to use per-cpu rx buffers. The first patch is just a refactor to prepare for the second one. The second one allocates percpu buffers if the following conditions are met: - CPU number is less or equal 4 - no port is using jumbo frames If the following conditions are not met at load time, of jumbo frame is enabled later on, the shared allocation is reverted. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-02mvpp2: percpu buffersMatteo Croce
Every mvpp2 unit can use up to 8 buffers mapped by the BM (the HW buffer manager). The HW will place the frames in the buffer pool depending on the frame size: short (< 128 bytes), long (< 1664) or jumbo (up to 9856). As any unit can have up to 4 ports, the driver allocates only 2 pools, one for small and one long frames, and share them between ports. When the first port MTU is set higher than 1664 bytes, a third pool is allocated for jumbo frames. This shared allocation makes impossible to use percpu allocators, and creates contention between HW queues. If possible, i.e. if the number of possible CPU are less than 8 and jumbo frames are not used, switch to a new scheme: allocate 8 per-cpu pools for short and long frames and bind every pool to an RXQ. When the first port MTU is set higher than 1664 bytes, the allocation scheme is reverted to the old behaviour (3 shared pools), and when all ports MTU are lowered, the per-cpu buffers are allocated again. Signed-off-by: Matteo Croce <mcroce@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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