summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-03-31dt-bindings: pinctrl: xway: drop the deprecated compatible stringsAleksander Jan Bajkowski
This code are marked as deprecated since kernel 4.5[1]. Downstream OpenWRT and upstream switched to the new string compatible 7 years ago. The old compatible strings can safely be dropped. [1] commit be14811c03cf ("pinctrl/lantiq: introduce new dedicated devicetree bindings") Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230330212225.10214-2-olek2@wp.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-31pinctrl: xway: drop the deprecated compatible stringsAleksander Jan Bajkowski
This code are marked as deprecated since kernel 4.5[1]. Downstream OpenWRT and upstream switched to the new string compatible 7 years ago. The old compatible strings can safely be dropped. [1] commit be14811c03cf ("pinctrl/lantiq: introduce new dedicated devicetree bindings") Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Link: https://lore.kernel.org/r/20230330212225.10214-1-olek2@wp.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-31dt-bindings: pinctrl: Drop unneeded quotesRob Herring
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Hector Martin <marcan@marcan.st> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> #rockchip Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230330200402.2731992-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-31pinctrl: amd: Add fields for interrupt status and wake statusMario Limonciello
If the firmware has misconfigured a GPIO it may cause interrupt status or wake status bits to be set and not asserted. Add these to debug output to catch this case. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230328174231.8924-3-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-31pinctrl: amd: Adjust debugfs outputMario Limonciello
More fields are to be added, so to keep the display from being too busy, adjust it. 1) Add a header to all columns 2) Except for interrupt, when fields have no data show empty 3) Remove otherwise blank whitespace Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230328174231.8924-2-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-30pinctrl: renesas: core: Drop unneeded #ifdef CONFIG_OFGeert Uytterhoeven
As the of_node member of struct device always exists, and there is a dummy of of_device_get_match_data() for the !CONFIG_OF case, there is no longer a need to protect code using these interfaces with an #ifdef. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/55d72ce46b43ec2f41681cb5ba7ca7fcebdb98d1.1679416005.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a7779: Add PWM pins, groups, and functionsGeert Uytterhoeven
Add pins, groups, and functions for the PWM Timers on the Renesas R-Car H1 (R8A7779) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cea9723e9c3df4b1408750caa38886aac1fab5f7.1679329090.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a7779: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up handling for the R-Car H1 SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dd966cfc916ef881051ec53bc3393dce7eea8e03.1679328215.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: Annotate sentinels in tablesGeert Uytterhoeven
It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Hence drop all such commas. Add comments to clarify the purpose of the empty elements. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/845f1d8285dd44522af1b0f429d4c6bd4759eb9e.1678272180.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sourcesGeert Uytterhoeven
Add support for configuring the I/O voltage levels of the Ethernet AVB and Ethernet TSN pins on the R-Car V4H SoC. "PIN_VDDQ_AVB[012]" and "PIN_VDDQ_TSN0" can be configured for 1.8V or 2.5V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c046e0be7d26302061d7aa629180a451734ddf8f.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a77995: Add support for AVB power-sourceGeert Uytterhoeven
Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car D3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8f9164487715d8a4898ca651038c0b4d5013764c.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a77990: Add support for AVB power-sourceGeert Uytterhoeven
Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car E3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/57883cd2d94c7919dc0f0db07cf6169ca89538e6.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a77980: Add support for AVB/GE power-sourcesGeert Uytterhoeven
Add support for configuring the I/O voltage levels of the Ethernet AVB and Gigabit Ethernet pins on the R-Car V3H SoC. "PIN_VDDQ_AVB" and "PIN_VDDQ_GE" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3c26c4f3735a6d071685c507c065172e63af5d70.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a77970: Add support for AVB power-sourceGeert Uytterhoeven
Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car V3M SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/eb4db82bdeb67507a1a77f63b9d90280d6f38ba4.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levelsGeert Uytterhoeven
Currently, the Renesas pin control driver supports pins that can switch their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. However, some SoCs have pins that can switch between 1.8V and 2.5V. Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE capability and voltage level flags by a 2-bit field, to cover three possible I/O voltage switching options. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flagGeert Uytterhoeven
Commit 537db25ca330dce0 ("pinctrl: renesas: Add I/O voltage level flag") introduced new flags to support pins that can switch their voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. The old SH_PFC_PIN_CFG_IO_VOLTAGE flag was retained to avoid having to change existing drivers. Replace SH_PFC_PIN_CFG_IO_VOLTAGE by SH_PFC_PIN_CFG_IO_VOLTAGE_18_33, to make the voltage configuration explicit, and to prepare for the advent of support for more voltage levels. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ae5f879c093f3e3cd50ba1495975bccfad81237b.1678271030.git.geert+renesas@glider.be
2023-03-30pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resumeGeert Uytterhoeven
The POC Control Register 0 (POCCTRL0) on R-Car D3 is not registered in the pinmux_ioctrl_regs[] array. Hence it is not saved/restored during suspend/resume, and its contents may be lost after s2ram. This went unnoticed when improving suspend/resume support in commit d92ee9cf8ec8d7fe ("pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume"). Fix this by moving the pinmux_ioctrl_regs[] array up, and adding the POCCTRL0 register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d17402b83b1f3fa0f572527c0382027bccb86205.1678271030.git.geert+renesas@glider.be
2023-03-29pinctrl: mcp23s08: Implement gpio bulk functionsUwe Kleine-König
To speed up some usecases implement reading and writing several IO lines at once. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230324164957.485924-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-29pinctrl: mcp23s08: Rename and change function that wraps regmap_update_bits()Uwe Kleine-König
The semantic of mcp_set_mask() was surprising to me when I first read that driver. So it was unexpected that in the call mcp_set_mask(mcp, MCP_OLAT, mask, value); value was a bool. Make the function a thinner wrapper around regmap_update_bits() and rename it to also have a similar name. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230324164957.485924-2-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-29Merge branch 'ib-qcom-quad-spi' into develLinus Walleij
2023-03-29pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLEDouglas Anderson
The Qualcomm pinctrl driver has been violating the documented meaning of PIN_CONFIG_INPUT_ENABLE. That documentation says: Note that this does not affect the pin's ability to drive output. ...yet the Qualcomm driver's sole action when asked to "enable input" on a pin is to disable its output. The Qualcomm driver's implementation stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Let's change the Qualcomm driver to move us in the right direction. As part of this: 1. We'll now support PIN_CONFIG_OUTPUT_ENABLE 2. We'll still support using PIN_CONFIG_INPUT_ENABLE to disable a pin's output (in violation of the docs) with a big comment in the code. This is needed because old device trees have "input-enable" in them and, in some cases, people might need the old behavior. While we could programmatically change all old device trees, it doesn't really hurt to keep supporting the old behavior and we're _supposed_ to try to be compatible with old device trees anyway. It can also be noted that the PIN_CONFIG_INPUT_ENABLE handling code seems to have purposefully ignored its argument. That means that old boards that had _either_ "input-disable" or "input-enable" in them would have had the effect of disabling a pin's output. While we could change this behavior, since we're only leaving the PIN_CONFIG_INPUT_ENABLE there for backward compatibility we might as well be fully backward compatible. NOTE: despite the fact that we'll still support PIN_CONFIG_INPUT_ENABLE for _setting_ config, we take it away from msm_config_group_get(). This appears to be only used for populating debugfs and fixing debugfs to "output enabled" where relevant instead of "input enabled" makes more sense and has more truthiness. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230323102605.8.Id740ae6a993f9313b58add6b10f6a92795d510d4@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-29dt-bindings: pinctrl: qcom: Add output-enableDouglas Anderson
In the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") we allowed setting "output-disable" for TLMM pinctrl states. Let's also add "output-enable". At first blush this seems a needless thing to do. Specifically: - In Linux (and presumably any other OSes using the same device trees) the GPIO/pinctrl driver knows to automatically enable the output when a GPIO is changed to an output. Thus in most cases specifying "output-enable" is superfluous and should be avoided. - If we need to set a pin's default state we already have "output-high" and "output-low" and these properties already imply "output-enabled" (at least on the Linux Qualcomm TLMM driver). However, there is one instance where "output-enable" seems like it could be useful: sleep states. It's not uncommon to want to configure pins as inputs (with appropriate pulls) when the driver controlling them is in a low power state. Then we want the pins back to outputs when the driver wants things running normally. To accomplish this we'd want to be able to use "output-enable". Then the "default" state could have "output-enable" and the "sleep" state could have "output-disable". NOTE: in all instances I'm aware of, we'd only want to use "output-enable" on pins that are configured as "gpio". The Qualcomm documentation that I have access to says that "output-enable" only does something useful when in GPIO mode. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230323102605.7.I7874c00092115c45377c2a06f7f133356956686e@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-29dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enableDouglas Anderson
As evidenced by the Qualcomm TLMM Linux driver, the TLMM IP block in Qualcomm SoCs has a bit to enable/disable the output for a pin that's configured as a GPIO but _not_ a bit to enable/disable an input buffer. Current device trees that are specifying "input-enable" for pins managed by TLMM are either doing so needlessly or are using it to mean "output-disable". Presumably the current convention of using "input-enable" to mean "output-disable" stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Given that there's no other use for "input-enable" for TLMM, we can still handle old device trees in code, but let's encourage people to move to the proper / documented property by updating the bindings. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-27dt-bindings: pinctrl: Convert Amlogic Meson pinctrl bindingHeiner Kallweit
Convert Amlogic Meson pin controller binding to yaml. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://lore.kernel.org/r/dd29c1b7-05db-dd98-df40-20a238d89a96@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-27pinctrl: s32cc: Use generic struct data to describe pin functionChester Lin
Replace struct s32_pmx_func with generic struct pinfunction since they have the same data fields. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-5-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-27pinctrl: s32cc: embed generic struct pingroupChester Lin
Use generic data structure to describe pin control groups in S32 SoC family and drop duplicated struct members. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-4-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-27pinctrl: s32cc: refactor pin config parsingChester Lin
Move common codes into smaller inline functions and remove argument checks that are not actually used by pull up/down bits in the S32 MSCR register. Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-3-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-27pinctrl: s32: refine error/return/config checks and simplify driver codesChester Lin
Improve error/return code handlings and config checks in order to have better reliability and simplify driver codes such as removing/changing improper macros, blanks, print formats and helper calls. Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-2-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-27Merge tag 'renesas-pinctrl-for-v6.4-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.4 - Add pin groups for audio on R-Car V4H, - Drop support for the obsolete R-Car H3 ES1.* (R8A77950) SoC, - Miscellaneous fixes and improvements.
2023-03-23pinctrl: Use of_property_present() for testing DT property presenceRob Herring
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230310144721.1544669-1-robh@kernel.org [Dropped hunk hitting drivers/pinctrl/renesas/pinctrl.c] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19pinctrl: mlxbf3: Add pinctrl driver supportAsmaa Mnebhi
NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs or take the default hardware functionality. Add a driver for the pin muxing. Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230315215027.30685-3-asmaa@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: qcom,sc8280xp-tlmm: allow 'bias-bus-hold'Johan Hovold
The controller supports 'bias-bus-hold' so add it to the binding. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230316105800.18751-1-johan+linaro@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: qcom,qcm2290-tlmm: Allow input-enableKonrad Dybcio
Allow the common input-enable. This was missed with the initial submission. Fixes: 5147022214db ("dt-bindings: pinctrl: qcom: Add QCM2290 pinctrl bindings") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230314222705.2940258-1-konrad.dybcio@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19pinctrl: qcom: Add IPQ9574 pinctrl driverDevi Priya
Add pinctrl definitions for the TLMM of IPQ9574 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20230316072940.29137-5-quic_devipriy@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: qcom: Add support for IPQ9574Devi Priya
Add new binding document for pinctrl on IPQ9574 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20230316072940.29137-4-quic_devipriy@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19pinctrl: qcom: Add SM7150 pinctrl driverDanila Tikhonov
Add pinctrl driver for TLMM block found in SM7150 SoC. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20230311212114.108870-3-danila@jiaxyga.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: qcom: Add SM7150 pinctrl bindingDanila Tikhonov
Add device tree binding Documentation details for Qualcomm SM7150 TLMM device Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230311212114.108870-2-danila@jiaxyga.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19MAINTAINERS: move ralink pinctrl to mediatek mips pinctrlArınç ÜNAL
The Ralink pinctrl driver is now under the name of MediaTek MIPS pin controller. Move the maintainer information accordingly. Add dt-binding schema files. Add linux-mediatek@lists.infradead.org as an associated mailing list. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230317213011.13656-22-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: mt7620: split bindingArınç ÜNAL
The MT7628 and MT7688 SoCs contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,mt76x8-pinctrl.yaml. Remove mediatek,mt76x8-pinctrl from mt7620. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-21-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: ralink: rt305x: split bindingArınç ÜNAL
The RT3352 and RT5350 SoCs each contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to ralink,rt3352-pinctrl.yaml and ralink,rt5350-pinctrl.yaml. Remove ralink,rt3352-pinctrl and ralink,rt5350-pinctrl from rt305x. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-20-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: mt7986: fix patternProperties regexArınç ÜNAL
Set second level patternProperties to '^.*mux.*$' and '^.*conf.*$' on mediatek,mt7986-pinctrl.yaml to be on par with other schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-19-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: drop quotes from referred schemasArınç ÜNAL
Drop the quotes from the referred schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-18-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: fix pinmux header locationArınç ÜNAL
Fix the location of the pinmux header files mentioned on the schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-17-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: {mediatek,ralink}: fix formattingArınç ÜNAL
Change the style of description properties to plain style where there's no need to preserve the line endings, and vice versa. Fix capitalisation and indentation. Fit the schemas to 80 columns for each line. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-16-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: fix naming inconsistencyArınç ÜNAL
Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek" to address the naming inconsistency. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-15-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: mt8195: rename to mediatek,mt8195-pinctrlArınç ÜNAL
Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-14-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: mt8192: rename to mediatek,mt8192-pinctrlArınç ÜNAL
Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-13-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: mt8186: rename to mediatek,mt8186-pinctrlArınç ÜNAL
Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-12-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: mediatek: mt6795: rename to mediatek,mt6795-pinctrlArınç ÜNAL
Rename mediatek,pinctrl-mt6795.yaml to mediatek,mt6795-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-11-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19dt-bindings: pinctrl: ralink: {mt7620,mt7621}: rename to mediatekArınç ÜNAL
Rename schemas of pin controllers for MediaTek MT7620 and MT7621 SoCs to be on par with other pin controllers for MediaTek SoCs. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230317213011.13656-10-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 19:47:37 +0000