| Age | Commit message (Collapse) | Author |
|---|
|
Pull watchdog update from Wim Van Sebroeck:
"Fix a kdump issue in hpwdt and a possible NULL dereference"
* git://www.linux-watchdog.org/linux-watchdog:
watchdog: Fix race condition in registration code
watchdog: Convert to devm_ioremap_resource()
|
|
Pull removal of GENERIC_GPIO from Grant Likely:
"GENERIC_GPIO now synonymous with GPIOLIB. There are no longer any
valid cases for enableing GENERIC_GPIO without GPIOLIB, even though it
is possible to do so which has been causing confusion and breakage.
This branch does the work to completely eliminate GENERIC_GPIO."
* tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux:
gpio: update gpio Chinese documentation
Remove GENERIC_GPIO config option
Convert selectors of GENERIC_GPIO to GPIOLIB
blackfin: force use of gpiolib
m68k: coldfire: use gpiolib
mips: pnx833x: remove requirement for GENERIC_GPIO
openrisc: default GENERIC_GPIO to false
avr32: default GENERIC_GPIO to false
xtensa: remove explicit selection of GENERIC_GPIO
sh: replace CONFIG_GENERIC_GPIO by CONFIG_GPIOLIB
powerpc: remove redundant GENERIC_GPIO selection
unicore32: default GENERIC_GPIO to false
unicore32: remove unneeded select GENERIC_GPIO
arm: plat-orion: use GPIO driver on CONFIG_GPIOLIB
arm: remove redundant GENERIC_GPIO selection
mips: alchemy: require gpiolib
mips: txx9: change GENERIC_GPIO to GPIOLIB
mips: loongson: use GPIO driver on CONFIG_GPIOLIB
mips: remove redundant GENERIC_GPIO select
|
|
Pull slave-dmaengine updates from Vinod Koul:
"This time we have dmatest improvements from Andy along with dw_dmac
fixes. He has also done support for acpi for dmanegine.
Also we have bunch of fixes going in DT support for dmanegine for
various folks. Then Haswell and other ioat changes from Dave and
SUDMAC support from Shimoda."
* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (53 commits)
dma: tegra: implement suspend/resume callbacks
dma:of: Use a mutex to protect the of_dma_list
dma: of: Fix of_node reference leak
dmaengine: sirf: move driver init from module_init to subsys_initcall
sudmac: add support for SUDMAC
dma: sh: add Kconfig
at_hdmac: move to generic DMA binding
ioatdma: ioat3_alloc_sed can be static
ioatdma: Adding write back descriptor error status support for ioatdma 3.3
ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap
ioatdma: Adding support for 16 src PQ ops and super extended descriptors
ioatdma: Removing hw bug workaround for CB3.x .2 and earlier
dw_dmac: add ACPI support
dmaengine: call acpi_dma_request_slave_channel as well
dma: acpi-dma: introduce ACPI DMA helpers
dma: of: Remove unnecessary list_empty check
DMA: OF: Check properties value before running be32_to_cpup() on it
DMA: of: Constant names
ioatdma: skip silicon bug workaround for pq_align for cb3.3
ioatdma: Removing PQ val disable for cb3.3
...
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
Pull thermal management update from Zhang Rui:
"The most important one is to build thermal core and governor and cpu
cooling code into one module. This fixes a regression that thermal
core does not work if it is built as module, since 3.7. I'll backport
them to stable kernel once those changes are in upstream.
The largest batch is the thermal kernel-doc & coding style
updates/cleanups from Eduardo.
Highlights:
- build all thermal framework code into one module to fix a
regression that thermal does not work if it is built as module.
- Marvell Armada 370/XP thermal sensor driver
- thermal core/cpu cooling kernel-doc & coding style updates and
cleanups.
- Add Eduardo Valentin as thermal sub-maintainer, both in mailing
list and patchwork. He will help me on arm thermal drivers."
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (68 commits)
thermal: db8500_cpufreq_cooling: remove usage of IS_ERR_OR_NULL()
thermal: thermal_core: remove usage of IS_ERR_OR_NULL
thermal: cpu_cooling: improve line breaking
thermal: cpu_cooling: alignment improvements
thermal: cpu_cooling: remove checkpatch.pl warning
thermal: cpu_cooling: remove trailing blank line
thermal: cpu_cooling: align on open parenthesis
thermal: cpu_cooling: standardize comment style
thermal: cpu_cooling: standardize end of function
thermal: cpu_cooling: remove trailing white spaces
Thermal: update documentation for thermal_zone_device_register
thermal: update kernel-doc for thermal_zone_device_register
thermal: update kernel-doc for create_trip_attrs
thermal: update kernel-doc for thermal_cooling_device_register
thermal: update kernel-doc for thermal_zone_unbind_cooling_device
thermal: update kernel-doc for thermal_zone_bind_cooling_device
thermal: use EXPORT_SYMBOL_GPL
thermal: rename notify_thermal_framework to thermal_notify_framework
thermal: update driver license
thermal: use strlcpy instead of strcpy
...
|
|
Enforce congruency of userspace shared mappings
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
|
Fix the one zillion warnings
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
|
This is the meat of the series which prevents any dcache alias creation
by always keeping the U and K mapping of a page congruent.
If a mapping already exists, and other tries to access the page, prev
one is flushed to physical page (wback+inv)
Essentially flush_dcache_page()/copy_user_highpage() create K-mapping
of a page, but try to defer flushing, unless U-mapping exist.
When page is actually mapped to userspace, update_mmu_cache() flushes
the K-mapping (in certain cases this can be optimised out)
Additonally flush_cache_mm(), flush_cache_range(), flush_cache_page()
handle the puring of stale userspace mappings on exit/munmap...
flush_anon_page() handles the existing U-mapping for anon page before
kernel reads it via the GUP path.
Note that while not complete, this is enough to boot a simple
dynamically linked Busybox based rootfs
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
|
This preps the low level dcache flush helpers to take vaddr argument in
addition to the existing paddr to properly flush the VIPT dcache
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
|
If a board isn't using twl4030, then dtc will complain about the missing
phandle (which is in twl4030.dtsi). Move the phy declaration to the dts
files.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Commit 6770b211 (ARM: OMAP2+: Export SoC information to userspace)
had some broken return value handling as noted by Russell King:
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR_OR_NULL(soc_dev)) {
+ kfree(soc_dev_attr);
+ return;
+ }
+
+ parent = soc_device_to_device(soc_dev);
+ if (!IS_ERR_OR_NULL(parent))
+ device_create_file(parent, &omap_soc_attr);
This is nonsense. For the first, IS_ERR() is sufficient. For the second,
tell me what error checking is required in the return value of this
function:
struct device *soc_device_to_device(struct soc_device *soc_dev)
{
return &soc_dev->dev;
}
when you've already determined that the passed soc_dev is a valid pointer.
If you read the comments against the prototype:
/**
* soc_device_to_device - helper function to fetch struct device
* @soc: Previously registered SoC device container
*/
struct device *soc_device_to_device(struct soc_device *soc);
if "soc" is valid, it means the "previously registered SoC device container"
must have succeeded and that can only happen if the struct device has been
registered. Ergo, there will always be a valid struct device pointer for
any registered SoC device container. Therefore, if soc_device_register()
succeeds, then the return value from soc_device_to_device() will always be
valid and no error checking of it is required.
Simples. The rule as ever applies here: get to know the APIs your using
and don't fumble around in the dark hoping that you'll get this stuff
right.
Fix it as noted by Russell.
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
|
|
|
|
Add new clockevent driver that uses the counter present on the MIPS
Global Interrupt Controller.
Signed-off-by: Raghu Gandham <Raghu.Gandham@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Various whitespace and #ifdef removals for GIC and R4K clocksources.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Reorganize some of the GIC clocksource driver code. Below is a list of
the various changes.
* No longer select CSRC_GIC by default for Malta platform.
* Limit choice for either the GIC or R4K clocksource, not both.
* Change location in Makefile.
* Created new 'gic_read_count' function in common 'irq-gic.c' file.
* Change 'git_hpt_read' function in 'csrc-gic.c' to use new function.
* Surround GIC specific code in Malta platform code with #ifdef's.
* Only initialize the GIC clocksource if it was selected. Original
code called it unconditionally if a GIC was found.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Move the global variable 'gic_frequency' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Move the global variable 'gic_present' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Add logic needed to handle unaligned accesses in MIPS16e mode.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
|
|
Add logic needed to properly calculate exceptions for delay slots
when in MIPS16e mode.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Add structures for all the MIPS16e instructions. Also add the
enumerations for all the bit fields for opcodes, functions, etc.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Optimise 'strnlen' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Optimise 'strlen' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Optimise 'strncpy' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Optimise 'memset' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
This adds the option to build the Linux kernel using only the
microMIPS ISA. The resulting kernel binary is, at a minimum,
20% smaller than using the MIPS32R2 ISA.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Partially revert commit e0c14a260d66ba35935600d6435940a566fe806b
and turn off LL/SC when building a pure microMIPS kernel. This is
a temporary fix until the cmpxchg assembly macro functions are
re-written to not use the HI/LO registers in address calculations.
Also add .insn in selected user access functions which would
otherwise produce ISA mode jump incompatibilities. This is also a
temporary fix.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Support vdso in microMIPS mode.
Signed-off-by: Douglas Leung <Douglas.Leung@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Add logic needed to handle unaligned accesses in microMIPS mode.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
|
|
Add logic needed to properly calculate exceptions for delay slots
when in microMIPS mode.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Add logic needed to do floating point emulation in microMIPS mode.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>
|
|
The macros did not properly take into account the ISA that
the kernel was being compiled with. A classic MIPS kernel
will have the standard 'uasm_i_##op' macro functions with
'MM_uasm_i_##op' macro functions for the microMIPS version.
A pure microMIPS kernel will have the standard macros with
'CL_uasm_i_##op' macro functions for the classic version.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Jump or branch target addresses have the first bit set. The
original mask did not take this into account and will cause
a field overflow warning for the target address when a jump
immediate instruction is built.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
|
Currently, the following instructions are translated:
- CACHE (indexed)
- CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations,
but still much faster than a trap.
- mfc0/mtc0: the virtual COP0 registers for the guest are implemented as
2-D array.
[COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0.
mfc0/mtc0 operations are transformed to load/stores.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
I get the following warning on boot:
------------[ cut here ]------------
WARNING: at drivers/base/core.c:575 device_create_file+0x9a/0xa0()
Hardware name: -[8737R2A]-
Write permission without 'store'
...
</snip>
Drilling down, this is related to dynamic channel ce_count attribute
files sporting a S_IWUSR mode without a ->store() function. Looking
around, it appears that they aren't supposed to have a ->store()
function. So remove the bogus write permission to get rid of the
warning.
Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: <stable@vger.kernel.org> # 3.[89]
[ shorten commit message ]
Signed-off-by: Borislav Petkov <bp@suse.de>
|
|
use 16M data cplb map on BF60x to avoid too much dcplb miss overhead
cleanup cplb info
Signed-off-by: Steven Miao <realmz6@gmail.com>
|
|
Nothing semantical
* simplify the alignement code by using & operation only
* rename variables clearly as paddr
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
|
Microblaze requires to enable IRQ in cpu_idle loop.
It should be the part of this patch:
"microblaze: Use generic idle loop"
(sha1: e962bb9e9cf73b8c8893c95903e791dd5ec19fb4)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
vaddr used to index the cache was clipped from the wrong end, and thus
would potentially fail to flush the correct lines.
The problem was dorment for so long because up until the recent
optimizations it was only used for ptrace break-point only flushes.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
|
|
With the patch to support MMUv3, the base address for the loaded
binary image has changed, and a fix was applied to the U-Boot image.
This fixes the RedBoot image.
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
This fixes the following lockdep splat:
[ 66.460000] =================================
[ 66.460000] [ INFO: inconsistent lock state ]
[ 66.460000] 3.9.0-rc5-00161-ga48dd49 #4 Not tainted
[ 66.460000] ---------------------------------
[ 66.460000] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage.
[ 66.460000] swapper/1 [HC0[0]:SC1[1]:HE1:SE0] takes:
[ 66.460000] (timer_lock){+.?...}, at: [<d0006cde>] rs_poll+0x12/0xdc
[ 66.460000] {SOFTIRQ-ON-W} state was registered at:
[ 66.460000] [<d00421f0>] lock_acquire+0xec/0x13c
[ 66.460000] [<d01ea036>] _raw_spin_lock+0x3a/0x84
[ 66.460000] [<d0006c8c>] rs_open+0x18/0x58
[ 66.460000] [<d0139ea2>] tty_open+0x262/0x3cc
[ 66.460000] [<d00942e0>] chrdev_open+0x8c/0xe0
[ 66.460000] [<d00907b2>] do_dentry_open$isra$16+0x10e/0x190
[ 66.460000] [<d0091141>] finish_open+0x39/0x48
[ 66.460000] [<d009a0b4>] do_last$isra$34+0x6c4/0x824
[ 66.460000] [<d009a27a>] path_openat+0x66/0x310
[ 66.460000] [<d009a53a>] do_filp_open+0x16/0x44
[ 66.460000] [<d0091445>] do_sys_open+0xd5/0x13c
[ 66.460000] [<d00914be>] sys_open+0x12/0x18
[ 66.460000] [<d0413ffc>] kernel_init_freeable+0xe4/0x12c
[ 66.460000] [<d01e2a9c>] kernel_init+0xc/0x9c
[ 66.460000] [<d00044fc>] ret_from_kernel_thread+0x8/0xc
[ 66.460000] irq event stamp: 132542
[ 66.460000] hardirqs last enabled at (132542): [<d01ea2ec>] _raw_spin_unlock_irq+0x30/0x44
[ 66.460000] hardirqs last disabled at (132541): [<d01ea11e>] _raw_spin_lock_irq+0xe/0x8c
[ 66.460000] softirqs last enabled at (132234): [<d0017d32>] __do_softirq+0x216/0x2a4
[ 66.460000] softirqs last disabled at (132539): [<d0018024>] irq_exit+0x38/0x40
[ 66.460000]
[ 66.460000] other info that might help us debug this:
[ 66.460000] Possible unsafe locking scenario:
[ 66.460000]
[ 66.460000] CPU0
[ 66.460000] ----
[ 66.460000] lock(timer_lock);
[ 66.460000] <Interrupt>
[ 66.460000] lock(timer_lock);
[ 66.460000]
[ 66.460000] *** DEADLOCK ***
[ 66.460000]
[ 66.460000] 1 lock held by swapper/1:
[ 66.460000] #0: (((&serial_timer))){+.-...}, at: [<d001c65c>] call_timer_fn+0x0/0x1f0
[ 66.460000]
Stack: d7c2fac0 00000018 00000004 00000001 d7c2faa0 00000004 00000006 d7c2fa90
9003e87c d7c2fae0 d7c30000 d025a87c 00000001 0000000f 00000000 d7c2fac0
9004005d d7c2fb10 d7c30000 d7c30338 00000001 00000001 00000000 d7c30338
[ 66.460000] Call Trace:
[ 66.460000] [<d01e4f93>] print_usage_bug$part$26+0x1c3/0x1c8
[ 66.460000] [<d003e87c>] mark_lock+0x2b4/0x440
[ 66.460000] [<d004005d>] __lock_acquire+0x54d/0x16c4
[ 66.460000] [<d00421f0>] lock_acquire+0xec/0x13c
[ 66.460000] [<d01ea036>] _raw_spin_lock+0x3a/0x84
[ 66.460000] [<d0006cde>] rs_poll+0x12/0xdc
[ 66.460000] [<d001c71a>] call_timer_fn+0xbe/0x1f0
[ 66.460000] [<d001cd90>] run_timer_softirq+0x198/0x1f4
[ 66.460000] [<d0017c30>] __do_softirq+0x114/0x2a4
[ 66.460000] [<d0018024>] irq_exit+0x38/0x40
[ 66.460000] [<d00046c0>] do_IRQ+0x44/0x48
[ 66.460000] [<d0005c58>] do_interrupt+0x4c/0x54
[ 66.460000] [<d0003c80>] common_exception_return+0x0/0x5c
[ 66.460000] [<d006682c>] free_pcppages_bulk+0x254/0x308
[ 66.460000]
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.
This was overlooked in the commit
2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.
do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
IRQs are disabled when PS.EXCM is set or PS.INTLEVEL is equal to or
higher than LOCKLEVEL.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
Definition of CALLER_ADDR* through __builtin_return_address makes
compiler insert calls to __xtensa_libgcc_window_spill, which in turn
makes fast_syscall_spill_registers syscall that clobbers registers when
called from the kernel mode, leading to invalid opcode exceptions on
return to userspace.
Provide definition for CALLER_ADDR0 as MAKE_PC_FROM_RA(a0, a1) and in
case CONFIG_FRAME_POINTER is enabled extract CALLER_ADDR{1-3} from
stack.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
|
- remove unused asm parameters;
- fix EXCM bit setting in the PS SR during _spill_registers call.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
|
