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2021-10-26pinctrl: intel: Kconfig: Add configuration menu to Intel pin controlCai Huoqing
Adding a configuration menu to hold many Intel pin control drivers helps to make the display more concise. Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-26pinctrl: tegra: Use correct offset for pin groupPrathamesh Shete
Function tegra_pinctrl_gpio_request_enable() and tegra_pinctrl_gpio_disable_free() uses pin offset instead of group offset, causing the driver to use wrong offset to enable gpio. Add a helper function tegra_pinctrl_get_group() to parse the pin group and determine correct offset. Signed-off-by: Kartik K <kkartik@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211025110959.27751-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-25pinctrl: core: fix possible memory leak in pinctrl_enable()Yang Yingliang
I got memory leak as follows when doing fault injection test: unreferenced object 0xffff888020a7a680 (size 64): comm "i2c-mcp23018-41", pid 23090, jiffies 4295160544 (age 8.680s) hex dump (first 32 bytes): 00 48 d3 1e 80 88 ff ff 00 1a 56 c1 ff ff ff ff .H........V..... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<0000000083c79b35>] kmem_cache_alloc_trace+0x16d/0x360 [<0000000051803c95>] pinctrl_init_controller+0x6ed/0xb70 [<0000000064346707>] pinctrl_register+0x27/0x80 [<0000000029b0e186>] devm_pinctrl_register+0x5b/0xe0 [<00000000391f5a3e>] mcp23s08_probe_one+0x968/0x118a [pinctrl_mcp23s08] [<000000006112c039>] mcp230xx_probe+0x266/0x560 [pinctrl_mcp23s08_i2c] If pinctrl_claim_hogs() fails, the 'pindesc' allocated in pinctrl_register_one_pin() need be freed. Cc: stable@vger.kernel.org Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 950b0d91dc10 ("pinctrl: core: Fix regression caused by delayed work for hogs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20211022014323.1156924-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-25pinctrl: bcm2835: Allow building driver as a moduleFlorian Fainelli
Update the pinctrl-bcm2835 driver to support being built as as a module by converting it to a module_platform_driver() with the appropriate module license, authors and description. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Link: https://lore.kernel.org/r/20211019221127.1953001-1-f.fainelli@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-25pinctrl: equilibrium: Fix function addition in multiple groupsRahul Tanwar
Ignore the same function with multiple groups. Fix a typo in error print. Fixes: 1948d5c51dba ("pinctrl: Add pinmux & GPIO controller driver for a new SoC") Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com> Link: https://lore.kernel.org/r/20211020093815.20870-1-rtanwar@maxlinear.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24pinctrl: tegra: Add pinmux support for Tegra194Prathamesh Shete
This change adds pinmux table entries for Tegra194 Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211018121815.3017-2-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24pinctrl: tegra: include lpdr pin propertiesSuresh Mangipudi
Update lpdr pin-property for supported pins. lpdr property help disable most basic driver fingers leaving only minimal base driver finger. Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211018121815.3017-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24pinctrl: mediatek: add support for MT7986 SoCSam Shih
This commit includes pinctrl driver for Mediatek MT7986 The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih <sam.shih@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20211022124036.5291-3-sam.shih@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24dt-bindings: pinctrl: update bindings for MT7986 SoCSam Shih
This updates bindings for MT7986 pinctrl driver. The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211022124036.5291-2-sam.shih@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24pinctrl: microchip sgpio: use reset driverHoratiu Vultur
On lan966x platform when the switch gets reseted then also the sgpio gets reseted. The fix for this is to extend also the sgpio driver to call the reset driver which will be reseted only once by the first driver that is probed. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20211018085754.1066056-3-horatiu.vultur@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add reset bindingHoratiu Vultur
This describes the new binding which allows to call a reset driver from the pinctrl-microchip-sgpio driver. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211018085754.1066056-2-horatiu.vultur@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cellsDmitry Baryshkov
Stop specifying individual interrupts properties. Use #interrupt-cells instead as we are switching qcom,spmi-mpp and qcom,ssbi-mpp to hierarchical IRQ setup. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-18-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chipDmitry Baryshkov
spmi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the spmi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-17-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17pinctrl: qcom: spmi-mpp: hardcode IRQ countsDmitry Baryshkov
The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,spmi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-16-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chipDmitry Baryshkov
ssbi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-15-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17pinctrl: qcom: ssbi-mpp: hardcode IRQ countsDmitry Baryshkov
The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,ssbi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-14-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17dt-bindings: pinctrl: qcom,pmic-mpp: Convert qcom pmic mpp bindings to YAMLDmitry Baryshkov
Convert Qualcomm PMIC MPP bindings from .txt to .yaml format. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-2-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17pinctrl: samsung: support ExynosAutov9 SoC pinctrlChanho Park
Add pinctrl data for ExynosAuto v9 SoC. - GPA0, GPA1: 10, External wake up interrupt - GPQ0: 2, XbootLDO, Speedy PMIC I/F - GPB0, GPB1, GPB2, GPB3: 29, I2S 7 CH - GPF0, GPF1, GPF2, GPF3,GPF4, GPF5, GPF6, GPF8: 52, FSYS - GPG0, GPG1, GPG2, GPG3: 25, GPIO x 24, SMPL_INT - GPP0, GPP1, GPP2, GPP3, GPP4, GPP5: 48, USI 12 CH Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20211008091443.44625-2-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211017171912.5044-1-krzysztof.kozlowski@canonical.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17dt-bindings: pinctrl: convert rockchip,pinctrl.txt to YAMLJohan Jonker
Convert rockchip,pinctrl.txt to YAML Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20211007144019.7461-1-jbx6244@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-17Merge tag 'renesas-pinctrl-for-v5.16-tag2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.16 (take two) - Add MediaLB pins on R-Car H3, M3-W/W+, and M3-N. - Miscellaneous fixes and improvements.
2021-10-15pinctrl: renesas: checker: Prefix common checker outputGeert Uytterhoeven
Add a "sh_pfc: " prefix to common checker output that is not yet prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for easier grepping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: checker: Fix bias checks on SoCs with pull-down only pinsGeert Uytterhoeven
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be checked. In addition, sh_pfc_check_bias_reg() does not handle such entries. Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/29526d06fa223cffd785cdb264b756a202b11cea.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: checker: Move overlapping field checkGeert Uytterhoeven
Move the check for overlapping drive register fields from sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for other register types, too. This requires passing the covered register bits to sh_pfc_check_reg(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9d75057200890bbf31e226ffcc4514ecc5bc2c34.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: checker: Fix off-by-one bug in drive register checkGeert Uytterhoeven
The GENMASK(h, l) macro creates a contiguous bitmask starting at bit position @l and ending at position @h, inclusive. This did not trigger any error checks, as the individual register fields cover at most 3 of the 4 available bits. Fixes: 08df16e07ad0a1ec ("pinctrl: sh-pfc: checker: Add drive strength register checks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8f82d6147fbe3367d4c83962480e97f58d9c96a2.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: Fix save/restore on SoCs with pull-down only pinsGeert Uytterhoeven
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be saved/restored during PSCI system suspend. Fortunately this does not trigger on any supported system yet, as PSCI is only used on R-Car Gen3 and RZ/G2 systems, which all have separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers. Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Note that a register controlling both pull-up and pull-down pins would be saved and restored twice, which is harmless. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/59d2fbddff685b6a7a82ff17d2b37633e30e8860.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: r8a779[56]x: Add MediaLB pinsAndrey Gusakov
This adds pins, groups, and functions for MediaLB devices on Renesas R-Car H3 and M3-W/N SoCs. Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211007200250.20661-1-nikita.yoush@cogentembedded.com [geert: Fix automotive handling] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-14pinctrl: gemini: fix typosDu Huanpeng
Signed-off-by: Du Huanpeng <dhu@hodcarrier.org> Link: https://lore.kernel.org/r/1633879405-11658-1-git-send-email-dhu@hodcarrier.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-14pinctrl: stm32: do not warn when 'st,package' is absentFabien Dessenne
Since the 'st,package' property is optional, outputting the "No package detected" warning-level log when the property is absent is unsuitable. Remove that log. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20211008122454.617556-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-13pinctrl: uniphier: Add UniPhier NX1 pinctrl driverKunihiko Hayashi
Add pin configuration and pinmux support for UniPhier NX1 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633518606-8298-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-13dt-bindings: pinctrl: uniphier: Add NX1 pinctrl bindingKunihiko Hayashi
Update pinctrl binding document for UniPhier NX1 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633518606-8298-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-13pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and PXs3 SoCsKunihiko Hayashi
Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633518606-8298-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-13pinctrl: qcom: spmi-gpio: Add compatible for PM6350Luca Weiss
Add support for the GPIO controller in the pm6350 PMIC. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20211007212444.328034-6-luca@z3ntu.xyz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-13dt-bindings: pinctrl: qcom,pmic-gpio: Add compatible for PM6350Luca Weiss
Add pmic-gpio compatible string for pm6350 pmic. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20211007212444.328034-5-luca@z3ntu.xyz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-03Merge tag 'renesas-pinctrl-for-v5.16-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.16 - Fix duplicate port register on RZ/G2L, - A minor improvement.
2021-10-03pinctrl: mediatek: add rsel setting on MT8195Zhiyong Tao
I2C pins's resistance value can be controlled by rsel register. This patch provides rsel (resistance selection) setting on MT8195 Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210924080632.28410-6-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-03pinctrl: mediatek: support rsel featureZhiyong Tao
This patch supports rsel(resistance selection) feature for I2C pins. It provides more resistance selection solution in different ICs. It provides rsel define and si unit solution by identifying "mediatek,rsel_resistance_in_si_unit" property in pio dtsi node. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-03pinctrl: mediatek: fix coding styleZhiyong Tao
Fix Camel spelling coding style to avoid checkpatch warning in a following patch. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210924080632.28410-4-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-03dt-bindings: pinctrl: mt8195: change pull up/down descriptionZhiyong Tao
For supporting SI units in "bias-pull-down" & "bias-pull-up", change pull up/down description and add "mediatek,rsel_resistance_in_si_unit" description. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20210924080632.28410-3-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-03dt-bindings: pinctrl: mt8195: add rsel defineZhiyong Tao
This patch adds rsel define for mt8195. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-03pinctrl: qcom: spmi-gpio: add support to enable/disable outputSubbaraman Narayanamurthy
Currently, if the GPIO is configured as output in the bootloader and user changes the mode to input in HLOS, it would end up getting configured as input/output. Functionally, this is fine; however, there may be some requirements where the output needs to be disabled so that it can be used only for input. Add support to enable/disable output mode through "output-enable" or "output-disable" pinctrl properties. Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631588246-4811-3-git-send-email-quic_subbaram@quicinc.com [Drop copyright change which is already upstrean in -rcN] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-24pinctrl: renesas: rzg2l: Fix missing port register 21hBiju Das
Remove the duplicate port register 22h and replace it with missing port register 21h. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922074140.22178-1-biju.das.jz@bp.renesas.com Fixes: c4c4637eb57f2a25 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-23dt-bindings: pinctrl: qcom-pmic-gpio: Add output-{enable,disable} propertiesSubbaraman Narayanamurthy
Add support for the pinconf DT property output-enable, output-disable so that output can be enabled/disabled. Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1631588246-4811-2-git-send-email-quic_subbaram@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-23pinctrl: qcom: Add QCM2290 pinctrl driverShawn Guo
It's a porting of pinctrl-scuba driver from CAF msm-4.19 kernel. The egpio and wake bits are removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923033224.29719-3-shawn.guo@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-23dt-bindings: pinctrl: qcom: Add QCM2290 pinctrl bindingsShawn Guo
Add device tree bindings for QCM2290 pinctrl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210923033224.29719-2-shawn.guo@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-23pinctrl: qcom: Add SM6350 pinctrl driverKonrad Dybcio
This adds pincontrol driver for tlmm block found in SM6350 SoC This patch is based on downstream copyleft code. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923161450.15278-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-23dt-bindings: pinctrl: qcom: Add SM6350 pinctrl bindingsKonrad Dybcio
Add device tree binding Documentation details for Qualcomm SM6350 pinctrl driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210923161450.15278-1-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-18pinctrl: qcom: msm8226: fill in more functionsLuca Weiss
Add the functions for QUP4 (spi, uart, uim & i2c), sdc3 and audio_pcm as derived from the downstream gpiomux configuration. Also sort the functions alphabetically, while we're at it. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210911232707.259615-2-luca@z3ntu.xyz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-17pinctrl: mediatek: mt8195: Add pm_opsZhiyong Tao
Setting this up will configure wake from suspend properly, and wake only for the interrupts that are setup in wake_mask, not all interrupts. Fixes: 6cf5e9ef362af824de2e4e8afb78d74537f1e3db ("pinctrl: add pinctrl driver on mt8195") Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210911071046.17349-2-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-17pinctrl: Fix spelling mistake "atleast" -> "at least"Colin Ian King
There is a spelling mistake in a dev_err message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210826123516.14441-1-colin.king@canonical.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-17pinctrl: nomadik: Kconfig: Remove repeated config dependencyCai Huoqing
remove it because "if (ARCH_U8500 || ARCH_NOMADIK)" is already used Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210825082536.2547-1-caihuoqing@baidu.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-31 21:56:33 +0000