summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-04-03drm/i915/tc: Add generic TC PHY connect/disconnect handlersImre Deak
Add generic handlers to connect/disconnect a PHY. Setting the TC mode to the target mode deducted from the HPD state and - if connecting to this mode fails - falling back to connecting to the default (TBT) mode are common to all platforms; move the logic for this from the ICL specific connect / disconnect handlers to the generic ones. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-12-imre.deak@intel.com
2023-04-03drm/i915/tc: Add TC PHY hook to read out the PHY HW stateImre Deak
Add a TC PHY hook to read out the PHY HW state on each platform, move the common parts to the generic helper. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-11-imre.deak@intel.com
2023-04-03drm/i915/tc: Add TC PHY hooks to get the PHY ready/owned stateImre Deak
Add TC PHY hooks to get the PHY ready/owned state on each platform, replacing the corresponding if ladder. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-10-imre.deak@intel.com
2023-04-03drm/i915/tc: Add TC PHY hook to get the PHY HPD live statusImre Deak
Add a table of TC PHY hooks which can be used to call platform specific TC PHY handlers, replacing the corresponding if ladders. Add the hook to retrieve the PHY's HPD live status. Move the common part fixing up the VBT legacy port flag to the generic helper. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-9-imre.deak@intel.com
2023-04-03drm/i915/tc: Move the intel_tc_port struct declaration to intel_tc.cImre Deak
Move the intel_tc_port struct to intel_tc.c for better isolation. This requires allocating the struct dynamically. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-8-imre.deak@intel.com
2023-04-03drm/i915/tc: Check for TC PHY explicitly in intel_tc_port_fia_max_lane_count()Imre Deak
Check explicitly if the port passed to intel_tc_port_fia_max_lane_count() has a TC PHY, instead of relying on the default TC mode value set for non-TC PHY ports. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-7-imre.deak@intel.com
2023-04-03drm/i915/tc: Move TC port fields to a new intel_tc_port structImre Deak
Move the TC port specific fields from intel_digital_port to a new intel_tc_port struct. Pass an intel_tc_port pointer to all static functions in intel_tc.c keeping dig_port accessible for these via a pointer stored in the new struct. The next patch will allocate the intel_tc_port dynamically, allowing moving the struct definition to intel_tc.c. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-6-imre.deak@intel.com
2023-04-03drm/i915/tc: Use the tc_phy prefix for all TC PHY functionsImre Deak
For consistency use the tc_phy prefix for all TC PHY functions. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-5-imre.deak@intel.com
2023-04-03drm/i915/tc: Rename tc_phy_status_complete() to tc_phy_is_ready()Imre Deak
For consistency rename tc_phy_status_complete() to tc_phy_is_ready() following the terminology of new platforms. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-4-imre.deak@intel.com
2023-04-03drm/i915/tc: Use the adlp prefix for ADLP TC PHY functionsImre Deak
Use the usual adlp prefix for all ADLP specific TC PHY functions. Other ADL platforms don't support TC. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-3-imre.deak@intel.com
2023-04-03drm/i915/tc: Group the TC PHY setup/query functions per platformImre Deak
Arrange the TC PHY HW state setup/query functions into platform specific and generic groups. This prepares for upcoming patches adding generic TC PHY handlers and platform specific hooks for these, replacing the corresponding if ladders. No functional changes. v2: Fix non kernel-doc multiline comments. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-2-imre.deak@intel.com
2023-04-03drm/i915/dsc: Add debugfs entry to validate DSC output formatsSwati Sharma
DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444). Also, new debugfs entry is created to enforce output format. This is required because of our driver policy. For ex. if a mode is supported in both RGB and YCbCr420 output formats by the sink, our policy is to try RGB first and fall back to YCbCr420, if mode cannot be shown using RGB. So, to test other output formats like YCbCr420 or YCbCr444, we need a debugfs entry (force_dsc_output_format) to force this output format. v2: -Func name changed to intel_output_format_name() (Jani N) -Return forced o/p format from intel_dp_output_format() (Jani N) v3: -output_format_str[] to remain static (Jani N) Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-8-suraj.kandpal@intel.com
2023-04-03drm/i915/vdsc: Check slice design requirementSuraj Kandpal
Add function to check if slice design requirements are being met as defined in Bspec: 49259 in the section Slice Design Requirement --v7 -remove full bspec link [Jani] -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid [Jani] --v8 -fix condition to check if slice width and height are of two -fix minimum pixel in slice condition --v10 -condition should be < rather then >= [Uma] Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-7-suraj.kandpal@intel.com
2023-04-03drm/i915/dsc: Fill in native_420 fieldSuraj Kandpal
Now that we have laid the groundwork for YUV420 Enablement we fill up native_420 field in vdsc_cfg and add appropriate checks wherever required. ---v2 -adding native_422 field as 0 [Vandita] -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in vds_cfg when native_420 is true ---v3 -adding display version check to solve igt issue --v7 -remove is_pipe_dsc check as its always true for D14 [Jani] --v10 -keep sink capability check [Jani] -move from !(x == y || w == z) to x !=y && w != z [Jani] --v11 -avoid native_420 computation if not gen14 [Uma] --v12 -fix state mismatch issue of compressed_bpp Cc: Uma Shankar <uma.shankar@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-6-suraj.kandpal@intel.com
2023-04-03drm/i915/dsc: Enable YCbCr420 for VDSCSuraj Kandpal
Implementation of VDSC for YCbCr420. Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c (Derived from C-Model, which is given along with DSC1.2a Spec from Vesa) intel_lookup_range_min/max_qp functons need to take into account the output format. Based on that appropriate qp table need to be chosen. Other rc_parameters need to be set where currently values for 444 format is hardcoded in calculate_rc_parameters( ). vdsc_cfg struct needs to be filled with output format information, where these are hardcoded for 444 format. Bspec: 49259 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-5-suraj.kandpal@intel.com
2023-04-03drm/i915/dsc: Adding the new registers for DSCSuraj Kandpal
Adding new DSC register which are introducted MTL onwards Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-4-suraj.kandpal@intel.com
2023-04-03drm/i915/dp: Check if DSC supports the given output_formatAnkit Nautiyal
Go with DSC only if the given output_format is supported. v2: Use drm helper to get DSC format support for sink. v3: remove drm_dp_dsc_compute_bpp. Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-3-suraj.kandpal@intel.com
2023-04-03drm/dp_helper: Add helper to check DSC support with given o/p formatAnkit Nautiyal
Add helper to check if the DP sink supports DSC with the given o/p format. v2: Add documentation for the helper. (Uma Shankar) v3: /** instead of /* (Uma Shankar) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-2-suraj.kandpal@intel.com
2023-03-31drm/i915: Define cursor chicken regVille Syrjälä
Define CUR_CHICKEN so we don't have to remember the offset. Looks like it's getting introduced in mtl. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329190445.13456-3-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-03-31drm/i915: Document that PLANE_CHICKEN are for tgl+Ville Syrjälä
Add tgl+ comments to the PLANE_CHICKEN registers which I apparently forgot to add when defining the registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329190445.13456-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-03-31drm/i915: Skip cursor when writing PLANE_CHICKENVille Syrjälä
Cursor is not a universal plane and thus doesn't have the PLANE_CHICKEN register. Skip it. Fixes: c5de248484af ("drm/i915/dpt: Add a modparam to disable DPT via the chicken bit") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329190445.13456-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-03-31drm/i915/psr: Implement Display WA #1136Jouni Högander
Implement Display WA #1136 for Pre-ICL. Bspec: 21664 v2: Handle disable psr in pre/post plane hooks Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-7-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Check that vblank is long enough for psr2Jouni Högander
Ensure vblank >= psr2 vblank where Psr2 vblank = PSR2_CTL Block Count Number maximum line count. Bspec: 71580, 49274 v2: Use calculated block count number maximum line count Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-6-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Add helpers for block count number handlingJouni Högander
Add helpers to make it more clear how PSR2_CTL[Block Count Number] is configured. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-5-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Implement Wa_14015648006Jouni Högander
PSR WM optimization should be disabled based on any wm level being disabled. Also same WA should be applied for ICL as well. Bspec: 71580 v5: - Set in pre plane hook and clear in post plane hook v4: - Handle mode change in psr enable/disable - Handle wm_level_disable changes separately in pre plane hook v3: - Split patch v2: - set/clear chicken bit in post_plane_update - apply for ICL as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-4-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006Jouni Högander
Wa_16013835468 is a separate from Wa_14015648006 and needs to be applied for display version 12. Fix this by removing all the references to Wa_14015648006 and apply Wa_16013835468 according to Bspec. Also move workaround into separate function as a preparation for Wa_14015648006 implementation. Bspec: 55378 v3: - apply for display version 12 only v2: - keep applying the wa in intel_psr_enable_source Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-3-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Unify pre/post hooksJouni Högander
pre/post hooks are doing things differently. Unify them. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-2-jouni.hogander@intel.com
2023-03-30drm/i915/mtl: Fix MTL stolen memory GGTT mappingDaniele Ceraolo Spurio
The PTEs expect the offset from the base of the fake LMEM region (i.e. the base of stolen) and not from the base of the DSM. Quoting the specs: "Driver will set the Device Memory bit = 1 in the PTE when pointing to a page in DSM and program the PTE with offset from LMEM_BAR. Device Memory Offset from LMEM_BAR is same as offset from BGSM." DSM starts 8MBs from BGSM, so we set dsm_base = 8MB. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328012430.2524330-1-daniele.ceraolospurio@intel.com
2023-03-30drm/i915/dsb: split out DSB regs to a separate fileJani Nikula
Clean up i915_reg.h by splitting out DSB regs to display/intel_dsb_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d74b3c564b2d080bf689b3360f1a5e62e47f2e7c.1678973283.git.jani.nikula@intel.com
2023-03-30drm/i915/fdi: split out FDI regs to a separate fileJani Nikula
Clean up i915_reg.h by splitting out FDI regs to display/intel_fdi_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bba37e46d767e2193d49d1d2e289040c6bf8229b.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915/aux: split out DP AUX regs to a separate fileJani Nikula
Clean up i915_reg.h by splitting out DP AUX regs to display/intel_dp_aux_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/aa93b34e786c5566acf8f053ffed96c160a23898.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915/tv: split out TV regs to a separate fileJani Nikula
Clean up i915_reg.h by splitting out TV regs to display/intel_tv_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/be4a946a7772f5b4483ad9e078cb62158849683e.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915/pps: split out PPS regs to a separate fileJani Nikula
Clean up i915_reg.h by splitting out PPS regs to display/intel_pps_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/80d66ee6d7e56153a0ab25640ac2dad239b1ef6e.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915: Make utility pin asserts more accurateVille Syrjälä
Only the PWM output mode of the utility pin is incompatible with DC6/LCPLL disable. Check for that specifically. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6609 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328164938.8193-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-03-29drm/i915: Use compressed bpp when calculating m/n value for DP MST DSCStanislav Lisovskiy
For obvious reasons, we use compressed bpp instead of pipe bpp for DSC DP SST case. Lets be consistent and use compressed bpp instead of pipe bpp, also in DP MST DSC case. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Fixes: d51f25eb479a ("drm/i915: Add DSC support to MST path") Link: https://patchwork.freedesktop.org/patch/msgid/20230327064217.24033-1-stanislav.lisovskiy@intel.com
2023-03-28drm/i915: remove unused config DRM_I915_UNSTABLEJani Nikula
Essentially this is a revert of commit d9d54a530a70 ("drm/i915: Put future HW and their uAPIs under STAGING & BROKEN"). We currently have no users for this config option. The last one was removed in commit 8c26491f5853 ("drm/i915: Kill the fake lmem support"). Drop it altogether; it's easy enough to resurrect if need arises. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327105330.312131-2-jani.nikula@intel.com
2023-03-28Merge drm/drm-next into drm-intel-nextRodrigo Vivi
Catch up with 6.3-rc cycle... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2023-03-28drm/i915/ips: Add i915_ips_false_color debugfs fileVille Syrjälä
Similar to FBC let's expose an debugfs file to control IPS false color. Enabling this provides an immediate visual feedback on whether IPS is working or not. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327133942.22063-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-03-28drm/i915/ips: Make IPS debugfs per-crtcVille Syrjälä
IPS is a per-pipe feature, so let's move the debugfs stuff under the crtc directory, and only register it when IPS is actually available. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327133942.22063-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-03-27Merge tag 'drm-rcar-next-20230325' of ↵Daniel Vetter
git://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux into drm-next Miscellaneous fixes and improvements for rcar-du Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230325204922.GD19335@pendragon.ideasonboard.com
2023-03-27drm/i915/reg: use the correct register to access SAGV block timeVinod Govindapillai
Wrong register address is used to read the SAG block time. Fix the register address according to the bspec. Bspec: 64608 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-3-vinod.govindapillai@intel.com
2023-03-27drm/i915/reg: fix QGV points register access offsetsVinod Govindapillai
Wrong offsets are calculated to read QGV point registers. Fix it to read from the correct registers. Bspec: 64602 Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-2-vinod.govindapillai@intel.com
2023-03-25drm: rcar-du: Fix a NULL vs IS_ERR() bugDan Carpenter
The drmm_encoder_alloc() function returns error pointers. It never returns NULL. Fix the check accordingly. Fixes: 7a1adbd23990 ("drm: rcar-du: Use drmm_encoder_alloc() to manage encoder") Signed-off-by: Dan Carpenter <error27@gmail.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2023-03-25drm: rcar-du: Write correct values in DORCR reserved fieldsLaurent Pinchart
The DORCR register controls the routing of clocks and data between DU channels within a group. For groups that contain a single channel, there's no routing option to control, and some fields of the register are then reserved. On Gen2 those reserved fields are documented as required to be set to 0, while on Gen3 and newer the PG1T, DK1S and PG1D reserved fields must be set to 1. The DU driver initializes the DORCR register in rcar_du_group_setup(), where it ignores the PG1T, DK1S and PG1D, and then configures those fields to the correct value in rcar_du_group_set_routing(). This hasn't been shown to cause any issue, but prevents certifying that the driver complies with the documentation in safety-critical use cases. As there is no reasonable change that the documentation will be updated to clarify that those reserved fields can be written to 0 temporarily before starting the hardware, make sure that the registers are always set to valid values. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2023-03-25drm: rcar-du: Rename DORCR fields to make them 0-basedLaurent Pinchart
The DORCR fields were documented in the R-Car H1 datasheet with 1-based named, and then got renamed to 0-based in Gen2. The 0-based names are used for Gen3 and Gen4, making H1 an outlier. Rename the field macros to make them 0-based, in order to increase readability of the code when comparing it with the documentation. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2023-03-25drm: rcar-du: Disable alpha blending for DU planes used with VSPLaurent Pinchart
When the input to a DU channel comes from a VSP, the DU doesn't perform any blending operation. Select XRGB8888 instead of ARGB8888 to ensure that the corresponding registers don't get written with invalid values. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2023-03-25drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3Laurent Pinchart
The ESCR and OTAR registers are not present in all DU channels on Gen3 SoCs. ESCR only exists in channels that can be routed to an LVDS or DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing those registers for other channels. This replaces the DU gen check, as Gen4 doesn't have LVDS or DPAD outputs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2023-03-25drm: rcar-du: lvds: Fix LVDS PLL disable on D3/E3Laurent Pinchart
On R-Car D3 and E3, the LVDS encoder provides the dot (pixel) clock to the DU, regardless of whether the LVDS output is used or not. When using the DPAD (RGB) output, the DU driver thus enables and disables the LVDS PLL manually, while when using the LVDS output, it lets the LVDS bridge driver handle the PLL configuration internally as part of the atomic enable and disable operations. This causes an issue when using the LVDS output. As bridges are disabled before CRTCs, the current implementation violates the enable/disable sequences documented in the hardware datasheet, which requires the dot clock to be enabled before the CRTC is started and disabled after it gets stopped. Fix the problem by enabling/disabling the LVDS PLL manually from the DU regardless of which output is used, and skipping the PLL handling in the LVDS bridge atomic enable and disable operations. This is however not enough. Disabling the LVDS encoder while leaving the PLL on still results in a vertical blanking wait timeout when disabling the DU. Investigation showed that the culprit is the LVEN bit. For an unclear reason, clearing the bit when disabling the LVDS encoder blocks vertical blanking interrupts. We thus have to delay disabling the whole LVDS encoder, not just disabling the PLL, until the DU is disabled. We could split the LVDS disable sequence by clearing the LVRES bit in the LVDS bridge atomic disable handler, and delaying the rest of the operations, in order to disable the LVDS output at bridge atomic disable time, before stopping the CRTC. This would make the code more complex, without a clear benefit, so keep the implementation simple(r). Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
2023-03-25drm: rcar-du: lvds: Move LVDS enable code to separate code sectionLaurent Pinchart
To prepare for a rework of the LVDS disable code, which will need to be called from rcar_lvds_pclk_disable(), move the LVDS enable code, currently stored in the __rcar_lvds_atomic_enable() function, to a separate code section separate from bridge operations. It will be then extended with the LVDS disable code. As part of this rework the __rcar_lvds_atomic_enable() function is renamed to rcar_lvds_enable() to more clearly indicate its purpose. No functional change intended. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
2023-03-25drm: rcar-du: lvds: Call function directly instead of through pointerLaurent Pinchart
When disabling the companion bridge in rcar_lvds_atomic_disable(), there's no need to go through the bridge's operations to call .atomic_disable(). Call rcar_lvds_atomic_disable() on the companion directly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 13:48:50 +0000