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2020-04-09drm/amd/display: Use config flag to disable dmcu obj creationWyatt Wood
[Why] When dmcub is the default we no longer wish to create the psr and dmcu objects. Currently a dc debug flag is used to implement this, but these flags aren't populated until after dcn21_resource_construct is called. This means the dmcub objects will never be created. Therefore we must use a dc config flag, which is populated before dc resource construct. [How] Add a dc config flag. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: Check power_down functions exist before callingSung Lee
[WHY] The power_down() function was only defined for specific asics and will crash the system if it is called by an asic with eDP connected that does not have it defined. [HOW] Add a check for the function's existence before calling it. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: Don't change mpcc tree for medium updates on DCN20 hwseqNicholas Kazlauskas
[Why] Overlay planes disappear when the plane's alpha blending mode or global opacity is modified. These are considered UPDATE_TYPE_MEDIUM and trigger the update_mpcc path in the DCN hardware sequencer. On DCN10 we have an "optimization" to avoid touching the blending tree on these updates, but this is actually required behavior based on how update_mpcc is structured. For full updates we acquire a MPCC for the plane, remove it if it already exists then reinsert it after with insert_plane. The call to insert_plane can take an optional mpcc to insert the new one above to preserve the current blending order. The update_mpcc hwseq function doesn't do this so the overlay gets sent to the very bottom of the tree. [How] Copy the check over from DCN10 to DCN20. The only time we need to actually touch the tree really is the full update, so this is also an optimization on top of the fix. Fixing the logic for insert_plane is rather simple (cache the bot_mpcc and pass it to insert_plane) but is a change that impacts most display usecases. For now stick with the optimization. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: blank dp stream before power off receiverXiaodong Yan
[why] power off dp receiver directly cause garbage during hw init [how] blank dp stream and then power off receiver Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: Power down hw blocks on bootSung Lee
[WHY] On headless boot a DIG may be turned on by VBIOS on RN. This leads to display_count being non-zero in hybrid graphics cases leading to SMU DISPLAY_OFF message not being sent. [HOW] Power down hardware on boot if seamless boot is not occurring (power_down_display_on_boot == 1) Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: Remove hdcp display state with mst fixIsabel Zhang
[Why] Due to previous code changes, displays transition from active to active and added state immediately, making it redundant to have both display states. Previous change to fix this caused HDCP to get into a bad state when monitor is connected to MST hub, this change fixes that issue. [How] Change code behavior so when a device is added successfully the state remains as active and when addition is unsuccessful change state to inactive. This removes need for added and active state. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: Implement abm config table copy to dmcubWyatt Wood
[Why] Driver must pass abm config table to dmub fw. This provides various parameters for abm functionality. [How] There is too much data to be passed in an inbox message, so we must pass this data using an indirect buffer. Copy the table to cw7 via x86, driver copies to fw_state structure. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: Program DSC before enabling linkNikola Cornij
[why] Link or DIG BE can't be exposed to a higher stream bandwidth than they can handle. When DSC is required to fit the stream into the link bandwidth, DSC has to be programmed before the link is enabled to ensure this. Without it, intermittent issues such as black screen after S3 or a hot-plug can be seen with DSC timings like 4k144Hz or 8k60Hz. [how] Move DSC programming from before enabling stream to before enabling link Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: prevent loop from occuring in pipe listJosip Pavic
[Why] If no free pipes are available, acquire_first_split_pipe is called to get a pipe to use. This call may alter the ordering of the pipes in the list so that, for example, the tail pipe changes. If acquire_first_split_pipe returns the tail pipe, we'll have free_pipe == tail_pipe. What tail_pipe refers to is not the current tail_pipe, but what was previously the tail pipe - i.e. prior to the call to acquire_first_split_pipe The logic that follows will link free_pipe to the tail pipe, referring to the current tail pipe. However, since tail_pipe is cached from before the call to acquire_first_split_pipe, the wrong tail pipe will be used, and it will end up being linked to itself, creating a loop that, if traversed, will result in a soft hang. [How] Do not cache the tail pipe. Instead, check the tail pipe after the call to acquire_first_split_pipe is made. Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/display: 3.2.78Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu/sriov add amdgpu_amdkfd_pre_reset in gpu resetJack Zhang
[PATCH 2/2] kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate Without this change, sriov tdr code path will never free those allocated memories and get memory leak. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdkfd Avoid destroy hqd when GPU is on resetJack Zhang
This reverts commit 5161bba4311f in order to split it into two different patches, and this will make it easier to understand. [PATCH 1/2] porting to gfx10 from commit 1b0bfcff463f390c40 ("drm/amdgpu: Avoid destroy hqd when GPU is on reset") Originally, MEC is touched without GPU initialized first. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: update RAS related dmesg printJohn Clements
prefix RAS error related dmesg print with pci device info Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: resolve mGPU RAS query instabilityJohn Clements
upon receiving uncorrectable error, query every GPU node for ras errors Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/amdgpu: Correct gfx10's CG sequenceChengming Gui
Incorrect CG sequence will cause gfx timedout, if we keep switching power profile mode (enter profile mod such as PEAK will disable CG, exit profile mode EXIT will enable CG) when run Vulkan test case(case used for test: vkexample). Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: add SPM golden settings for Navi12Tianci.Yin
Add RLC_SPM golden settings Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: add SPM golden settings for Navi14Tianci.Yin
Add RLC_SPM golden settings Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: add SPM golden settings for Navi10(v2)Tianci.Yin
Add RLC_SPM golden settings Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: Print UTCL2 client ID on a gpuvm faultOak Zeng
UTCL2 client ID is useful information to get which UTCL2 client caused the gpuvm fault. Print it out for debug purpose Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/powerplay: fix a typoNirmoy Das
Util -> Until Fixes: 567c8fc4a0d28b63f ("drm/amd/powerplay: implement the is_dpm_running()") Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu/vcn: add shared memory restore after wake up from sleep.James Zhu
VCN shared memory needs restore after wake up during S3 test. v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: Fix oops when pp_funcs is unset in ACPI eventAaron Ma
On ARCTURUS and RENOIR, powerplay is not supported yet. When plug in or unplug power jack, ACPI event will issue. Then kernel NULL pointer BUG will be triggered. Check for NULL pointers before calling. Signed-off-by: Aaron Ma <aaron.ma@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu/psp: dont warn on missing optional TA'sAlex Deucher
Replace dev_warn() with dev_info() and note that they are optional to avoid confusing users. The RAS TAs only exist on server boards and the HDCP and DTM TAs only exist on client boards. They are optional either way. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: rework sched_list generationNirmoy Das
Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: sync ring type and drm hw_ip typeNirmoy Das
Use AMDGPU_HW_IP_* to set amdgpu_ring_type enum values Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu/sriov add amdgpu_amdkfd_pre_reset in gpu resetJack Zhang
kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate Without this change, sriov tdr code path will never free those allocated memories and get memory leak. v2:add a bugfix for kiq ring test fail Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/display: fix the broken logic in dc_link.cYifan Zhang
Add missing braces. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/powerplay: avoid using pm_en before it is initializedTiecheng Zhou
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. so avoid using pm_en in pp_get_asic_baco_capability. Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/powerplay: implement the is_dpm_running()Prike Liang
As the pmfw hasn't exported the interface of SMU feature mask to APU SKU so just force on all the features to driver inquired interface at early initial stage. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/display: re-order asic declarationsShirish S
Fixes build error of: "use of undeclared identifier 'RENOIR_A0'" To fix the same, this patch re-orders the ASIC declarations accordingly. Fixes: 41ef3dcd86443fa ("drm/amd/display: Fix RV2 Variant Detection") Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Zhan Liu <zhan.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLKYuxian Dai
1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03amdgpu/drm: remove psp access on navi10 for sriovAlex Sierra
Navi ASICs don't require to access through PSP to osssys registers. This on SR-IOV configuration. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/display: Guard calls to hdcp_ta and dtm_taBhawanpreet Lakha
[Why] The buffer used when calling psp is a shared buffer. If we have multiple calls at the same time we can overwrite the buffer. [How] Add mutex to guard the shared buffer. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/display: remove mod_hdcp_hdcp2_get_link_encryption_status()Bhawanpreet Lakha
It is not being used, so remove it Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amd/dc: Kill dc_conn_log_hex_linux()Lyude Paul
DRM already supports tracing DPCD transactions, there's no reason for the existence of this function. Also, it prints one byte per-line which is way too loud. So, just remove it. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amd/amdgpu_dm/mst: Remove useless sideband tracingLyude Paul
We already trace DPCD reads/writes on both MST and SST, there's no reason to have this code here (plus, toggling these things with a define at the top of the file isn't how we do things in the kernel). Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn: fix spelling mistake "fimware" -> "firmware"Colin Ian King
There is a spelling mistake in a dev_err error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu: fix and cleanup amdgpu_gem_object_close v4Christian König
The problem is that we can't add the clear fence to the BO when there is an exclusive fence on it since we can't guarantee the the clear fence will complete after the exclusive one. To fix this refactor the function and also add the exclusive fence as shared to the resv object. v2: fix warning v3: add excl fence as shared instead v4: squash in fix for fence handling in amdgpu_gem_object_close Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: xinhui pan <xinhui.pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amd/display: code cleanup of dc_link file on func dc_link_constructMelissa Wen
Removes codestyle issues in dc_link file, on dc_link_construct and translate_encoder_to_transmitter as suggested by checkpatch.pl. Types covered: CHECK: Lines should not end with a '(' WARNING: Missing a blank line after declarations CHECK: Alignment should match open parenthesis CHECK: Comparison to NULL could be written CHECK: Logical continuations should be on the previous line CHECK: Blank lines aren't necessary after an open brace '{' Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amd/display: code cleanup on dc_link from is_same_edid to get_ddc_lineMelissa Wen
Removes codestyle issues on the file dc_link between is_same_edid and get_ddc_line as suggested by checkpatch.pl. Types covered: CHECK: Blank lines aren't necessary after an open brace '{' CHECK: Blank lines aren't necessary before a close brace '}' WARNING: braces {} are not necessary for single statement blocks CHECK: Comparison to NULL could be written CHECK: Lines should not end with a '(' CHECK: Alignment should match open parenthesis CHECK: Using comparison to false is error prone CHECK: Using comparison to true is error prone WARNING: Avoid multiple line dereference - prefer 'link->dpcd_caps.sink_count.bits.SINK_COUNT' CHECK: Unnecessary parentheses around WARNING: Missing a blank line after declarations Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amd/display: codestyle cleanup on dc_link file until detect_dp funcMelissa Wen
Removes codestyle issues on the file dc_link until detect_dp func as suggested by checkpatch.pl. Types covered: CHECK: Please don't use multiple blank lines CHECK: Comparison to NULL could be written ERROR: space required before the open parenthesis '(' CHECK: Alignment should match open parenthesis CHECK: Lines should not end with a '(' WARNING: please, no space before tabs WARNING: Comparisons should place the constant on the right side of the test WARNING: braces {} are not necessary for single statement blocks CHECK: Please don't use multiple blank lines Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amd/display: cleanup codestyle type BLOCK_COMMENT_STYLE on dc_linkMelissa Wen
Solve comments alignment problems on dc_link file Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu: enable VCN2.5 DPG mode for ArcturusJames Zhu
Enable VCN2.5 DPG mode for arcturus after below items are applied. ASD: 0x21000023 SOS: 0x17003B VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16 VBIOS: 23 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn2.5: Add firmware w/r ptr reset syncJames Zhu
Add firmware write/read point reset sync through shared memory Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn2.0: Add firmware w/r ptr reset syncJames Zhu
Add firmware write/read point reset sync through shared memory Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn: Add firmware share memory supportJames Zhu
Added firmware share memory support for VCN. Current multiple queue mode is enabled only. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn2.5: stall DPG when WPTR/RPTR resetJames Zhu
Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR resetJames Zhu
Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn: fix race condition issue for dpg unpause mode switchJames Zhu
Couldn't only rely on enc fence to decide switching to dpg unpaude mode. Since a enc thread may not schedule a fence in time during multiple threads running situation. v3: 1. Rename enc_submission_cnt to dpg_enc_submission_cnt 2. Add dpg_enc_submission_cnt check in idle_work_handler v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu/vcn: fix race condition issue for vcn startJames Zhu
Fix race condition issue when multiple vcn starts are called. v2: Removed checking the return value of cancel_delayed_work_sync() to prevent possible races here. v3: Add total_submission_cnt to avoid gate power unexpectedly. v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 16:03:28 +0000