summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2024-06-06drm/i915/display: include intel_step.h where neededJani Nikula
Include what you use. With this, we can drop the include along with xe_step.h from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/abee71a6c6edbd1a3ddf0f97838977e53feaa5ff.1717004739.git.jani.nikula@intel.com
2024-06-06drm/i915/display: include intel_uncore.h where neededJani Nikula
Include what you use. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bc3a722413e20db905671e58627ba6d757f41c63.1717004739.git.jani.nikula@intel.com
2024-06-06drm/i915/display: include i915_gpu_error.h where neededJani Nikula
Include what you use. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a5dbb8d46403761bd8518db45fa71dc55930d3cf.1717004739.git.jani.nikula@intel.com
2024-06-06drm/i915/display: include gt/intel_gt_types.h where neededJani Nikula
Include what you use. We need to move the compat intel_gt_types.h under gt subdir. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/df73c0934ad21f157714a41b33b81cebd2a523a6.1717004739.git.jani.nikula@intel.com
2024-06-06drm/i915/display: include gem/i915_gem_stolen.h where neededJani Nikula
Include what you use. We need to move the compat i915_gem_stolen.h under gem subdir. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6ac3480a8689fda5aaf4007cb604e06e939a03f7.1717004739.git.jani.nikula@intel.com
2024-06-05drm/i915: drop redundant W=1 warnings from MakefileJani Nikula
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default across the subsystem"), most of the extra warnings in the driver Makefile are redundant. Remove them. Note that -Wmissing-declarations and -Wmissing-prototypes are always enabled by default in scripts/Makefile.extrawarn. Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/490931748fa9a1dbac2bceda0c4b778240b10b58.1716471145.git.jani.nikula@intel.com
2024-06-05drm/i915: Protect CRC reg macro arguments for consistencyVille Syrjälä
It's probably a good idea to start protecting all macro arguments to avoid any cargo-cult mistakes when people go looking for examples of how to define these things. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915: Define the PIPE_CRC_EXP registersVille Syrjälä
I need a scratch register which fill the following requirements: - can be accessed via DSB - all the bits can be read/written - no serious side effects So far the only thing I could think of is the "expected CRC" register. Add the definition so I can use it. While I only need the hsw+ variant currently, let's define the older variants as well for completeness. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-7-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915: Document which platforms have which CRC registersVille Syrjälä
Sprinkle some comments around to indicate which CRC registers are valid for which platforms. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915: Add a separate definition for PIPE_CRC_RES_HSWVille Syrjälä
On hsw+ we only have one CRC result register, instead of the five we have on ivb, and some of the others have been repurposed to serve other CRC related purposes. Since the hsw+ vs. pre-hsw register operate quite differently let's add a separate definition for the hsw+ variant to make the situation a bit more clear. Also since we only use this from a hsw+ codepath there is no real benefit to be had with reusing the ivb register definition. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915: Regroup pipe CRC regsVille Syrjälä
Put all the definitions related to a single pipe CRC register in one place, instead of the current approach where things are spread all over the place. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE()Ville Syrjälä
PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid for IVB+ where pipe register blocks are equally spaced, so we can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for these. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915: Extract intel_pipe_crc_regs.hVille Syrjälä
The CRC registers are a pretty self contained bunch. Extract them to a separate header to declutter i915_reg.h. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-05drm/i915/dsb: Use intel_color_uses_dsb()Ville Syrjälä
Use intel_color_uses_dsb() instead of open coding it in intel_vblank_evade_init(). Make the logic around DSB a bit more isolated from the rest of the code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-5-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-06-05drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä
Allow the caller of intel_dsb_prepare() to determine which DSB engine (out of the three possible per pipe) to use. This will let us utilize multiple DSB engines during the same commit. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-4-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-06-05drm/i915/dsb: Move DSB ID definition to the headerVille Syrjälä
We're going to need to make the DSB ID visible outside the DSB code, so that we eg. can use multiple DSB engines in parallel. to that end move the definition to intel_dsb.h. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-3-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-06-05drm/i915/dsb: Polish the DSB ID enumVille Syrjälä
Namespace the DSB ID enum properly, and make the naming match other such enums in general. Also make the names 0 based as that's what Bspec uses for DSB (unlike eg. planes where it uses 1 based indexing). We'll throw out INVALID_DSB while at it since we have no use for it at the moment. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-2-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-06-04drm/i915: Fix assert on pending async-put power domain work when it requeues ↵Imre Deak
itself Commit dd839aa857eb ("drm/i915: Fix incorrect assert about pending power domain async-put work") fixed the assert about a pending work dropping a display power reference asynchronously, leading to the drm_WARN_ON(!queue_delayed_work(&power_domains->async_put_work)); warn next time around a power reference was put asynchronously, due to a stale instance of the work still being pending. However the fix didn't consider the case where multiple power reference was acquired and put, requiring the work to requeue itself. Extend the fix for this case as well canceling the pending instance of the work before it requeues itself. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10915 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240530105312.1016485-1-imre.deak@intel.com
2024-06-03drm/i915/psr: Add Early Transport into psr debugfs interfaceJouni Högander
We want to have sink Early Transport capability and usage in our psr debugfs status interface. v4: use su_region_et_enabled instead of psr2_su_region_et_valid v3: remove extra space from "PSR mode: disabled" v2: printout "Selective Update enabled (Early Transport)" instead of "Selective Update Early Transport enabled" Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-7-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfsJouni Högander
Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug debugfs interface is not allowed. This patch allows it. v3: - ensure psr is disabled/enabled if enable_psr2_su_region_et changes - remove extra space v2: ensure that fastset is performed when the bit changes Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-6-jouni.hogander@intel.com
2024-06-03drm/i915/display: Selective fetch Y position on Region Early TransportJouni Högander
Selective fetch Y position differs when Region Early Transport is used. Use formula from Bspec for this. Bspec: 68927 Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-5-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Use enable boolean from intel_crtc_state for Early TransportJouni Högander
When enabling Early Transport use intel_crtc_state->enable_psr2_su_region_et instead of psr2_su_region_et_valid. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-4-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Get Early Transport status in intel_psr_pipe_get_configJouni Högander
We are currently not getting Early Transport status information in intel_psr_pipe_get_config. Fix this. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-3-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Add Early Transport status boolean into intel_psrJouni Högander
Currently we are purely relying on psr2_su_region_et_valid. Add new boolean value into intel_psr struct indicating whether Early Transport is enabled or not and use it instead of psr2_su_region_et_valid for getting Early Transport status information. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-2-jouni.hogander@intel.com
2024-05-31MAINTAINERS: update i915 and xe entries for include/drm/intelJani Nikula
With all the Intel specific drm files under include/drm/intel, update the i915, xe, and the shared display entries. Do not discriminate based on file name pattern, just add the entire directory for all three entries. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Oded Gabbay <ogabbay@kernel.org> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Tvrtko Ursulin <tursulin@ursulin.net> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e0fdf28307bb3e457d8c67966c09c44cf7ff5783.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move i915_hdcp_interface.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5f53384118e33123d3c87b94cc8835360237698b.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move xe_pciids.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e19543f2ae978678c2ff814454f07c96ccd02175.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move i915_pciids.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a19cebc0f03588b9627dcaaebe69a9fef28c27f0.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move i915_pxp_tee_interface.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5c1626978d2552ef5732dcf9427c903046afb9c1.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move i915_drm.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also fix comment in intel_pci_config.h (Ilpo) Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0e344a72e9be596ac2b8b55a26fd674a96f03cdc.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move intel_lpe_audio.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2d645970a65cfd13e01fd8195b35bf9483ae9c2f.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move i915_component.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also change Documentation/gpu/i915.rst (Andi) Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a8c07233a8234858eb6711140482ef8db4c91cf4.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move i915_gsc_proxy_mei_interface.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/461662d528c3f327c81b764b7c883cd4519d8729.1717075103.git.jani.nikula@intel.com
2024-05-31drm: move intel-gtt.h under include/drm/intelJani Nikula
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ae224504d99cc6428da6dced9dcde2b7953624ef.1717075103.git.jani.nikula@intel.com
2024-05-31drm/i915: reduce includes in intel_clock_gating.cJani Nikula
With the refactoring in the file, some excessive includes were left behind and are now unnecessary. Remove. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240530100747.328631-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: drop unnecessary i915_reg.h includesJani Nikula
With the register header refactoring, some of the includes of i915_reg.h have become unnecessary. Remove. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240530100747.328631-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: remove intermediate _PCH_DP_* macrosJani Nikula
The intermediate macros are unused. Remove them. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0145043ff9767de93cc3dc5119f0e7152965ebe6.1716894910.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: move PCH DP AUX CH regs to intel_dp_aux_regs.hJani Nikula
Move the macros where they belong. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9bc3a7bb34edc5dc17ffcb2a9e64edcef8c7a7b8.1716894910.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: rearrange DP AUX register macrosJani Nikula
Follow the recommended style for grouping register macros. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8ace710d8a1edac7e1af1ed12122fb6bc68114e9.1716894910.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: remove unused DP AUX CH register macrosJani Nikula
The intermediate macros are no longer needed. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c97134b22d802ae82b19c299b79807ee60d9fae5.1716894909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915/gvt: use proper macros for DP AUX CH CTL registersJani Nikula
Use the proper helpers for DP AUX CH CTL registers, instead of reinventing the wheels. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f30d35f28ef106d6fb2faf100fe1c5e3a42dfa20.1716894909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Switch intel_usecs_to_scanlines() to 64bit mathsVille Syrjälä
Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(), with its 32bit maths, is currently limited to a few milliseconds. I want bigger numbers in DSB selftests, so switch over to 64bit maths. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Move intel_crtc_scanline_offset()Ville Syrjälä
I want to use intel_crtc_scanline_offset() in intel_crtc_scanline_to_hw(). Relocate intel_crtc_scanline_offset() a bit to avoid a forward declaration. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Simplify scanline_offset handling for gen2Ville Syrjälä
Currently intel_crtc_scanline_offset() is careful to always return a positive offset. That is not actually necessary as long as we take care of negative values when applying the offset in __intel_get_crtc_scanline(). This simplifies intel_crtc_scanline_offset(), and makes the scanline_offfset arithmetic more symmetric between the forward (__intel_get_crtc_scanline()) and reverse (intel_crtc_scanline_to_hw()) directions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Extract intel_mode_vtotal()Ville Syrjälä
We have several copies of code calculating the hardware's idea of vtotal. Pull that to a helper, similar to intel_mode_vblank_{start,end}(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Extract intel_mode_vblank_end()Ville Syrjälä
Extract intel_mode_vblank_end() in the same vein as intel_mode_vblank_start(). While we have only one use of this it seems nicer to unify the approach. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Reuse intel_mode_vblank_start()Ville Syrjälä
Replace a few hand rolled copies of intel_mode_vblank_start() with the real thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Plumb the full atomic state into skl_ddb_add_affected_planes()Ville Syrjälä
skl_ddb_add_affected_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. The wm counterpart (skl_wm_add_affected_planes()) already does things in the proper way. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Plumb the full atomic state into icl_check_nv12_planes()Ville Syrjälä
icl_check_nv12_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915/cdclk: Plumb the full atomic state deeperVille Syrjälä
Various parts of the cdclk code need access the full atomic state. Currently it's being dug out via the cdclk_state->base.state pointer, which is not great as that pointer isn't always valid. Instead plumb the full atomic state from the top so that it's clear that it is in fact valid. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 21:42:47 +0000