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AgeCommit message (Expand)Author
2024-05-22drm/i915: Polish sprite plane register definitionsVille Syrjälä
2024-05-22drm/i915: Document a few pre-skl primary plane platform dependenciesVille Syrjälä
2024-05-22drm/i915: Polish pre-skl primary plane registersVille Syrjälä
2024-05-22drm/i915: Extract i9xx_plane_regs.hVille Syrjälä
2024-05-22drm/i915: Move PIPEGCMAX to intel_color_regs.hVille Syrjälä
2024-05-22drm/i915: Add separate defines for cursor WM/DDB register bitsVille Syrjälä
2024-05-22drm/i915: Rename selective fetch plane registersVille Syrjälä
2024-05-22drm/i915: Simplify PIPESRC_ERLY_TPT definitionVille Syrjälä
2024-05-22drm/i915: Add separate define for SEL_FETCH_CUR_CTL()Ville Syrjälä
2024-05-22drm/i915: Clean up the cursor register definesVille Syrjälä
2024-05-22drm/i915: Add skl+ plane name aliases to enum plane_idVille Syrjälä
2024-05-22drm/i915/dpt: Make DPT object unshrinkableVidya Srinivas
2024-05-22drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+Ville Syrjälä
2024-05-22drm/i915/bmg: Load DMCGustavo Sousa
2024-05-22drm/i915/hdcp: Check mst_port to determine connector typeSuraj Kandpal
2024-05-22drm/i915/hdcp: Move aux assignment after connector type checkSuraj Kandpal
2024-05-22drm/i915: stop redefining INTEL_VGA_DEVICEJani Nikula
2024-05-22drm/i915/pciids: switch to xe driver style PCI ID macrosJani Nikula
2024-05-21MAINTAINERS: Move the drm-intel repo location to fd.o GitLabRyszard Knop
2024-05-20drm/i915/psr: PSR2_CTL[Block Count Number] not needed for LunarLakeJouni Högander
2024-05-20drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wideJouni Högander
2024-05-20drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68Jouni Högander
2024-05-17drm/i915/selftests: Set always_coherent to false when reading from CPUNirmoy Das
2024-05-16drm/i915: pass dev_priv explicitly to CURSURFLIVEJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CUR_CHICKENJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CUR_FBC_CTLJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CURSIZEJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPTJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CURPOSJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CURBASEJani Nikula
2024-05-16drm/i915: pass dev_priv explicitly to CURCNTRJani Nikula
2024-05-15drm/i915/pciids: don't include RPL-U PCI IDs in RPL-PJani Nikula
2024-05-15drm/i915/pciids: remove 12 from INTEL_TGL_IDS()Jani Nikula
2024-05-15drm/i915/pciids: remove 11 from INTEL_ICL_IDS()Jani Nikula
2024-05-15drm/i915/pciids: don't include WHL/CML PCI IDs in CFLJani Nikula
2024-05-15drm/i915/pciids: add INTEL_IVB_IDS()Jani Nikula
2024-05-15drm/i915/pciids: add INTEL_SNB_IDS()Jani Nikula
2024-05-15drm/i915/pciids: add INTEL_ILK_IDS(), use acronymJani Nikula
2024-05-15drm/i915/pciids: add INTEL_PNV_IDS(), use acronymJani Nikula
2024-05-15drm/i915: Handle SKL+ WM/DDB registers next to all other plane registersVille Syrjälä
2024-05-15drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()Ville Syrjälä
2024-05-15drm/i915: Extract skl_plane_{wm,ddb}_reg_val()Ville Syrjälä
2024-05-15drm/i915: Refactor skl+ plane register offset calculationsVille Syrjälä
2024-05-15drm/i915: Drop a few unwanted tabs from skl+ plane reg definesVille Syrjälä
2024-05-15drm/i915: Use REG_BIT for PLANE_WM bitsVille Syrjälä
2024-05-15drm/i915: Shuffle the skl+ plane register definitionsVille Syrjälä
2024-05-15drm/i915: Drop useless PLANE_FOO_3 register definesVille Syrjälä
2024-05-15drm/i915/gvt: Use PLANE_CTL and PLANE_SURF definesVille Syrjälä
2024-05-15drm/i915/gvt: Use the full PLANE_KEY*() definesVille Syrjälä
2024-05-15drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() defineVille Syrjälä
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 01:37:55 +0000