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2025-03-04arm64: dts: rockchip: Add hdmi for rk3576Andy Yan
Add hdmi and it's phy dt node for rk3576. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add vop for rk3576Andy Yan
Add VOP and VOP_MMU found on rk3576. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3588 boardsKrzysztof Kozlowski
Devicetree bindings for ES8388 audio codec expect the device to be marked as compatible with ES8328. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250304104200.76178-2-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3399 ROC PC PLUSKrzysztof Kozlowski
Devicetree bindings for ES8388 audio codec expect the device to be marked as compatible with ES8328. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250304104200.76178-1-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20CJonas Karlman
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard CH340B for debug console use. Add pinctrl for UART0 M0 pins used for serial console. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528Jonas Karlman
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node removed due to missing label reference to pcfg_output_low_pull_down. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04dt-bindings: soc: rockchip: Add RK3528 ioc grf sysconJonas Karlman
The GPIO is accessible via ioc grf syscon registers on RK3528. Add compatible string for RK3528 ioc grf syscon. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250228064024.3200000-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-28arm64: dts: rockchip: add usb typec host support to rk3588-jaguarHeiko Stuebner
Jaguar has two type-c ports connected to fusb302 controllers that can work both in host and device mode and can also run in display-port altmode. While these ports can work in dual-role data mode, they do not support powering the device itself as power-sink. This causes issues because the current infrastructure does not cope well with dual-role data without dual-role power. So add the necessary nodes for the type-c controllers as well as enable the relevant core usb nodes. So far host modes works reliably, but device-mode does not. So devicemode needs more investigation. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250228150853.329175-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-28arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588Sebastian Reichel
Enabling the GPU power domain requires that the GPU regulator is enabled. The regulator is enabled at boot time, but gets disabled automatically when there are no users. This means the system might run into a failure state hanging the whole system for the following use cases: * if the GPU driver is being probed late (e.g. build as a module and firmware is not in initramfs), the regulator might already have been disabled. In that case the power domain is enabled before the regulator. * unbinding the GPU driver will disable the PM domain and the regulator. When the driver is bound again, the PM domain will be enabled before the regulator and error appears. Avoid this by adding an explicit regulator dependency to the power domain. Tested-by: Heiko Stuebner <heiko@sntech.de> Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com> Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 audio output for Orange Pi 5 UltraJimmy Hon
HDMI audio is available on the Orange Pi 5 Ultra HDMI1 TX port. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250222193332.1761-6-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 UltraJimmy Hon
Enable the only HDMI output port on the Orange Pi 5 Ultra Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Tested-By: Johannes Erdfelt <johannes@erdfelt.com> Link: https://lore.kernel.org/r/20250222193332.1761-5-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add Orange Pi 5 Ultra boardJimmy Hon
The RK3588 Single Board Computer includes - eMMC - microSD - UART - 2 PWM LEDs - RTC - RTL8125 network controller on PCIe 2.0x1. - M.2 M-key connector routed to PCIe 3.0x4 - PWM controlled heat sink fan. - 2 USB2 ports - lower USB3 port - upper USB3 port with OTG capability - Mali GPU - SPI NOR flash - Mask Rom button - Analog audio using es8388 codec via the headset jack and onboard mic - HDMI1 - HDMI IN the vcc5v0_usb30 regulator shares the same enable gpio pin as the vcc5v0_usb20 regulator. The Orange Pi 5 Ultra is a single board computer powered by the Rockchip RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped for HDMI IN. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Tested-By: Johannes Erdfelt <johannes@erdfelt.com> Link: https://lore.kernel.org/r/20250222193332.1761-4-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 UltraJimmy Hon
Add devicetree binding for the Xunlong Orange Pi 5 Ultra board. The Orange Pi 5 Ultra is a single board computer powered by the Rockchip RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped for HDMI IN. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250222193332.1761-3-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and UltraJimmy Hon
The Orange Pi 5 Plus and Orange Pi 5 Max have 2SK3018s attached to the PWM LEDs. The Orange Pi 5 Ultra does not, and thus needs the PWM polarity inverted. Also remove the model/compatible from the dtsi. It should be at the board level only. Fixes: c600d252dc52 ("arm64: dts: rockchip: Add Orange Pi 5 Max board") Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250222193332.1761-2-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITXJianfeng Liu
Enable the HDMI port next to ethernet port. Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5BDetlev Casanova
HDMI audio is available on the Rock 5B HDMI TX ports. Enable it for both ports. Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add HDMI audio outputs for rk3588Detlev Casanova
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node as CODEC and the i2s5 device as CPU. Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is i2s6, but only added in the rk3588-extra.dtsi device tree as the second TX HDMI port is not available on base versions of the SoC. The simple-audio-card,mclk-fs value is set to 128 as it is done in the downstream driver. The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so that they can be used as audio codec nodes. Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1Cristian Ciocaltea
Add the necessary DT changes to enable the second HDMI output port on Rockchip RK3588 EVB1. While at it, switch the position of &vop_mmu and @vop to maintain the alphabetical order. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-5-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588Cristian Ciocaltea
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. The HDMI1 PHY PLL clock source cannot be added directly to vop node in rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an optional feature and its PHY node belongs to a separate (extra) DT file. Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its clocks & clock-names properties in the extra DT file. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588Cristian Ciocaltea
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4BAndy Yan
Enable USB3 OTG and it's related PHY node. And the PHY will also be shared with the upcoming DisplayPort controller. Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250223100757.73531-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Add UART clocks for RK3528 SoCYao Zi
Add missing clocks in UART nodes for RK3528 SoC. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Add clock generators for RK3528 SoCYao Zi
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is generated by internal Ethernet phy, a fixed clock node is added as a placeholder to avoid orphans. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26Merge branch 'v6.15-shared/clkids' into v6.15-armsoc/dts64Heiko Stuebner
2025-02-26dt-bindings: clock: Document clock and reset unit of RK3528Yao Zi
There are two types of clocks in RK3528 SoC, CRU-managed and SCMI-managed. Independent IDs are assigned to them. For the reset part, differing from previous Rockchip SoCs and downstream bindings which embeds register offsets into the IDs, gapless numbers starting from zero are used. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: disable I2C2 bus by default on RK3588 TigerQuentin Schulz
RK3588 Tiger routes I2C2 signals to the Q7 Camera FFC connector (P2) but nothing on the SoM itself is on that bus, therefore it'll be up to the adapter connected to the Q7 Camera FFC connector (P2) to enable the I2C2 controller, if need be. Thus, disable it by default. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-9-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSIQuentin Schulz
PX30 Ringneck only exposes I2C3 as LVDS_BLC_CLK/DAT on Q7 golden fingers but nothing is on that bus on the SoM itself. Therefore, let's enable the I2C3 bus where it makes sense, in the Haikou carrierboard DTS. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-8-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable Ethernet in Haikou carrierboard, not Puma DTSIQuentin Schulz
The signals are exposed on Q7 golden fingers but it's not a given that the carrierboard will have an Ethernet jack. So let's move the enabling of the Ethernet controller to the carrierboard DTS instead. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-7-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add EEPROM found on RK3399 Puma HaikouQuentin Schulz
The Haikou carrierboard has an EEPROM on LVDS_BLC_CLK/DAT which are signals that can carry either I2C or be used as HPD for eDP0/1. Only eDP0 is routed from RK3399 Puma SoM but only exposed on Haikou through the Video Connector, a fake PCIe connector. So to be able to use eDP one would need to use a Device Tree overlay. Therefore, let's default to having an EEPROM in Haikou carrierboard DTS. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-6-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable I2S0 in Haikou carrierboard, not Puma DTSIQuentin Schulz
I2S0 is routed to the Q7 golden fingers and, on Haikou carrierboard, to an I2S codec. Nothing aside from signal routing is done on the SoM, therefore it's the duty of the carrierboard to enable I2S0 whenever an I2S codec is present. Such is the case of the Haikou carrierboard, therefore let's migrate the enabling of this controller to the carrierboard DTS instead of the SoM DTSI. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-5-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: disable I2C6 on Puma DTSIQuentin Schulz
The bus is only exposed on Q7 Camera FFC connector which accepts external adapters such as Q7 Camera Demo. The enabling of I2C6 should therefore be done in the adapter Device Tree Overlay and not in the SoM DTSI, so let's disable it by default. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-4-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: move I2C6 from Haikou carrierboard to Puma DTSIQuentin Schulz
I2C6 is not exposed on Q7 golden fingers which is for routing signals to the carrierboard but on Q7 Camera connector, for routing signals to an additional adapter (e.g. Q7 Camera Demo adapter). Therefore, let's move the modification of I2C6 bus to Puma DTSI. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-3-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: move DDC bus from Haikou carrierboard to RK3399 Puma DTSIQuentin Schulz
The DDC bus is necessarily on I2C3, that's how it's exposed by RK3399 Puma on the Q7 golden fingers, so let's move it to the SoM DTSI instead. If the carrierboard doesn't route it for some reason, /delete-property/ can be used to remove it. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-2-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable UART5 on RK3588 Tiger HaikouQuentin Schulz
In its default configuration (SW2 on "UART1"), UART5 is exposed on the DB9 RS232/RS485 connector. While the same signals are also exposed on Q7_GPIO5 and Q7_GPIO6, a GPIO header, and thus could be used for other purposes, RK3399 Puma Haikou and PX30 Ringneck Haikou do enable the UART controller exposed on the DB9 connector, so let's keep consistency across our modules and enable it on RK3588 Tiger Haikou by default too. Add a comment while at it to explicit where this controller is routed to. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-1-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: Add Radxa ROCK 4D device treeStephen Chen
The Radxa ROCK 4D board is based on the Rockchip rk3576 SoC. The device tree adds support for basic devices: - UART - SD Card - Ethernet - USB - RTC It has 4 USB ports but only 3 are usable as the top left one is used for maskrom. It has a USB-C port that is only used for powering the board. Signed-off-by: Stephen Chen <stephen@radxa.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Link: https://lore.kernel.org/r/20250218160714.140709-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23dt-bindings: arm: rockchip: Add Radxa ROCK 4D boardDetlev Casanova
The board is based on the Rockchip rk3576 SoC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Link: https://lore.kernel.org/r/20250218160714.140709-2-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add rk3576 otp nodeHeiko Stuebner
This adds the otp node to the rk3576 soc devicetree including the individual fields we know about. Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de
2025-02-23arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapterQuentin Schulz
This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with RK3399 Puma SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. Its main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet because the expected clock rate by the driver cannot be exactly reached by the clock driver). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-5-310c0b9a3909@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapterQuentin Schulz
This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with PX30 Ringneck SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. Itss main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet because the expected clock rate by the driver cannot be exactly reached by the clock driver). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-4-310c0b9a3909@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 ↵Quentin Schulz
Ringneck The HAIKOU-LVDS-9904379 adapter is an adapter for PX30 Ringneck with the Haikou carrierboard. It is to be inserted in the fake PCIe slot labelled Video Connector. This adapter expects an Admatec 9904379 1024x600 LVDS display with backlight and touchscreen. An EEPROM is also found on the adapter. This adds support for this adapter on PX30 Ringneck when inserted in Haikou carrierboard. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-3-310c0b9a3909@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-16arm64: dts: rockchip: Add rng node to RK3588Nicolas Frattaroli
Add the RK3588's standalone hardware random number generator node to its device tree, and enable it. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com [changed reset-id to its numeric value while the constant makes its way through the crypto tree] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-14arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PCHeiko Stuebner
As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72 cores, four Cortex-A53 cores and Mali-G52 MC3 GPU. Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to use UFS 2.0 storage. Video Output options are a HDMI port, a DSI connector as well as Display- Port via the TypeC connector (all of them not yet supported). Networking options are a Low-profile Gigabit Ethernet RJ45 port with Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module. USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C and it comes with 40-pin GPIO header Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250210205126.1173631-3-heiko@sntech.de
2025-02-14dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC bindingHeiko Stuebner
Add devicetree binding for the ROC-RK3576-PC SBC. The board is based on the RK3576 SoC (4*Cortex-A72 + 4*Cortex-A53). Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250210205126.1173631-2-heiko@sntech.de
2025-02-14arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 ↵Quentin Schulz
Jaguar The Pre-ICT tester adapter connects to RK3588 Jaguar SBC through its proprietary Mezzanine connector. It exposes a PCIe Gen2 1x M.2 connector and two proprietary camera connectors. Support for the latter will come once the rest of the camera stack is supported. Additionally, the adapter loops some GPIOs together as well as route some GPIOs to power rails. This adapter is used for manufacturing RK3588 Jaguar to be able to test the Mezzanine connector is properly soldered. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dragan Simic <dsimic@manjaro.org> # Makefile Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250211-pre-ict-jaguar-v6-4-4484b0f88cfc@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-14arm64: dts: rockchip: add overlay tests for Rock 5B PCIe overlaysQuentin Schulz
According to commit 40658534756f ("arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode"), Rock 5B can operate in PCIe endpoint mode. For that to work, the rk3588-rock-5b-pcie-ep.dtbo overlay needs to be applied on Rock 5B base Device Tree. If that Rock 5B is connected to another Rock 5B, the latter needs to apply the rk3588-rock-5b-pcie-srns.dtbo overlay. In order to make sure the overlays are still valid in the future, let's add a validation test by applying the overlays on top of the main base at build time. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250211-pre-ict-jaguar-v6-3-4484b0f88cfc@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-14arm64: dts: rockchip: add overlay test for Edgeble NCM6A/NCM6BQuentin Schulz
The Edgeble NCM6A/NCM6B can have WiFi modules connected and this is handled via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay")). Despite the name of the overlay, it applies to both NCM6A and NCM6B[1]. In order to make sure the overlay is still valid in the future, let's add a validation test by applying the overlay on top of the main bases at build time. [1] https://lore.kernel.org/linux-rockchip/CA+VMnFyom=2BmJ_nt-At6hTQP0v+Auaw-DkCVbT9mjndMmLKtQ@mail.gmail.com/ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250211-pre-ict-jaguar-v6-2-4484b0f88cfc@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-14arm64: dts: rockchip: add overlay test for WolfVision PF5Quentin Schulz
The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO Expander board connected to it. Therefore, let's generate an overlay test so the application of the two overlays are validated against the base DTB. Suggested-by: Michael Riesch <michael.riesch@wolfvision.net> Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250211-pre-ict-jaguar-v6-1-4484b0f88cfc@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-12arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 MaxJimmy Hon
Enable the second HDMI output port on the Orange Pi 5 Max Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250109051619.1825-5-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-11arm64: dts: rockchip: linewrap gmac assigned-clocks on Quartz64 Model A/B ↵Dragan Simic
files a bit Going over the 80-column width limit, and using all 100 columns, is intended for improving code readability. This wasn't the case in a few places in the Quartz64 Model A/B board dts files, so let's reflow them a bit, to both obey the 80-column limit and make them a bit more readable. No intended functional changes are introduced by these changes. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/7eea4ebdb19d5f43d24074a166e6c46bb5424d46.1739218324.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-11arm64: dts: rockchip: remove rk3588 optee nodeChris Morgan
Remove Optee node from rk3588 devicetree. When Optee is present and used the node will be added automatically by U-Boot when CONFIG_OPTEE_LIB=y and CONFIG_SPL_ATF_NO_PLATFORM_PARAM is not set. When Optee is not present or used, the node will trigger a probe that generates a (harmless) message on the kernel log. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20250130181005.6319-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 05:51:14 +0000