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2024-12-30arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6qdl-apalis: Change to "adi,force-bt656-4"Fabio Estevam
According to adv7180.yaml, the correct property name is "adi,force-bt656-4". Update it accordingly to fix several dt-schema warnings: adv7280@21: 'adv,force-bt656-4' does not match any of the regexes: ... imx6qdl-apalis.dtsi is the only in-tree kernel user of this property. BSD does have a adv7180 driver, so should not be impacted. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6sx: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The regulator handling was introduced by commit `966d73152078 (usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty, 2024-07-26)`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6sl: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The 3p0 regulator handling was introduced by commit 966d73152078 ("usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6qdl: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The 3p0 regulator handling was introduced by commit 966d73152078 ("usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Drop interrupt from WM1811 codecArtur Weber
This was initially copied from the Midas DTSI, but there is no proof that the same interrupt is also used on the Tab 3. The pin listed as the interrupt here is GPIO_HDMI_CEC on the Midas, but for the Tab 3 it is the headset button GPIO - GPIO_EAR_SEND_END. Drop the interrupt, since there is no proof that it is used. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-5-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Add MCLK2 clock to WM1811 codec configArtur Weber
In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K, which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in mainline as S2MPS11_CLK_BT. Add the MCLK2 clock to the WM1811 codec clock property to properly describe the hardware. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-4-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Fix headset mic, add jack detectionArtur Weber
Set up headset mic bias regulator and add the necessary properties to the samsung,midas-audio node to allow for headset jack detection. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-3-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: socfpga: remove non-existent DAC from CycloneV devkitConor Dooley
There is no Rohm DAC on the CycloneV devkit according to the online documentation for it that I could find, and it definitely does not have a dh2228fv as this device does not actually exist! Remove the DAC node from the devicetree as it is not acceptable to pretend to have a device on a board in order to bind the spidev driver in Linux. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240717-partake-antivirus-3347e415fb7d@spud Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmodeAndré Draszik
When the serial console is enabled, we need to disable power delivery since serial uses the SBU1/2 pins and appears to confuse the TCPCI, resulting in endless interrupts. For now, change the DT such that the serial console continues working. Note1: We can not have both typec-power-opmode and new-source-frs-typec-current active at the same time, as otherwise DT binding checks complain. Note2: When using a downstream DT, the Pixel boot-loader will modify the DT accordingly before boot, but for this upstream DT it doesn't know where to find the TCPCI node. The intention is for this commit to be reverted once an updated Pixel boot-loader becomes available. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCiAndré Draszik
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO) * charger * fuel gauge * TCPCi While in the same package, TCPCi and Fuel Gauge have separate I2C addresses, interrupt lines and interrupt status registers and can be treated independently. The TCPCi is required to detect and handle connector orientation in Pixel's USB PHY driver, and to configure the USB controller's role (host vs device). This change adds the TCPCi part as it can be independent and doesn't need a top-level MFD. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-23arm64: dts: mediatek: mt8183-kukui-jacuzzi: Drop pp3300_panel voltage settingsChen-Yu Tsai
The pp3300_panel fixed regulator is just a load switch. It does not have any regulating capabilities. Thus having voltage constraints on it is wrong. Remove the voltage constraints. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20241030070224.1006331-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-23arm64: dts: mediatek: Set mediatek,mac-wol on DWMAC node for all boardsNícolas F. R. A. Prado
Due to the mediatek,mac-wol property previously being handled backwards by the dwmac-mediatek driver, its use in the DTs seems to have been inconsistent. Now that the driver has been fixed, correct this description. All the currently upstream boards support MAC WOL, so add the mediatek,mac-wol property to the missing ones. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20241109-mediatek-mac-wol-noninverted-v2-2-0e264e213878@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-22arm64: dts: exynos: Add initial support for Samsung Galaxy S9 (SM-G960F)Markuss Broks
Samsung Galaxy S9 (SM-G960F), codenamed starlte, is a mobile phone released in 2017. It has 4GB of RAM, 64GB of UFS storage, Exynos9810 SoC and 1440x2960 Super AMOLED display. This initial device tree enables the framebuffer pre-initialised by bootloader and physical buttons of the device, with more support to come in the future. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241214-exynos9810-v4-2-4e91fbbc2133@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22arm64: dts: exynos: Add Exynos9810 SoC supportMarkuss Broks
Exynos 9810 is an ARMv8 mobile SoC found in various Samsung devices, such as Samsung Galaxy S9 (starlte), S9 Plus (star2lte), Note 9 (crownlte) and perhaps others. Add minimal support for this SoC, including basic stuff like: - PSCI for bringing up secondary cores - ARMv8 generic timer - GPIO and pinctrl. The firmware coming with the devices based on this SoC is buggy and doesn't configure CNTFRQ_EL0, as required by spec, so it's needed to hardcode the frequency in the timer node. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241214-exynos9810-v4-1-4e91fbbc2133@gmail.com [krzysztof: Rename and move PMU nodes to proper sorting position] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22arm64: dts: exynos850-e850-96: Specify reserved secure memory explicitlySam Protsenko
Instead of carving out the secure area in 'memory' node, let's describe it in 'reserved-memory'. That makes it easier to understand both RAM regions and particular secure world memory region. Originally the device tree was created in a way to make sure it was well aligned with the way LittleKernel bootloader modified it. But later it was found the LittleKernel works fine with properly described reserved regions, so it's possible now to define those in a cleaner way. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20241211033027.12985-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22arm64: dts: exynos990: Add a PMU node for the third clusterUmer Uddin
Since we have a PMU compatiable for Samsung's Mongoose cores now, drop the comment that explains the lack of it and define the node. Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241214115855.49138-2-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-21arm64: dts: allwinner: h313: enable DVFS for Tanix TX1Andre Przywara
The merging of the Tanix TX1 .dts file overlapped with the introduction of the CPU OPP .dtsi file, so the TX1 wasn't covered by the patch enabling DVFS for all boards. Add the missing include of that OPP .dtsi file, to allow the box to run at up to 1.3GHz, and enable power saving by using lower OPPs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20241215212533.12707-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-12-20Merge tag 'renesas-dts-for-v6.14-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.14 - Add more serial (SCIF), power monitor, ADC, and sound support for the RZ/G3S SoC and the RZ/G3S SMARC SoM and development board, - Add support for the R-Car V4H ES3.0 (R8A779G3) SoC on the White Hawk Single development board, - Add display support for the R-Car V4M SoC and the Gray Hawk Single development board, - Add video capture support for the Gray Hawk Single development board, - Add initial support for the RZ/G3E (R9A09G047) SoC and the RZ/G3E SMARC SoM and Carrier-II EVK development board, - Add support for 5-port MATEnet on the Falcon Ethernet sub-board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (33 commits) arm64: dts: renesas: r9a09g047: Add I2C nodes arm64: dts: renesas: rzg3s-smarc: Add sound card arm64: dts: renesas: rzg3s-smarc: Enable SSI3 arm64: dts: renesas: Add da7212 audio codec node arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node arm64: dts: renesas: r9a08g045: Add SSI nodes arm64: dts: renesas: rzg3s-smarc-som: Enable ADC arm64: dts: renesas: r9a08g045: Add ADC node arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: falcon-ethernet: Describe PHYs connected on the breakout board arm64: dts: renesas: r8a779a0: Remove address- and size-cells from AVB[1-5] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants arm64: dts: renesas: gray-hawk-single: Add video capture support arm64: dts: renesas: gray-hawk-single: Add DisplayPort support arm64: dts: renesas: r8a779h0: Add display support ... Link: https://lore.kernel.org/r/cover.1734689803.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-20Merge tag 'stm32-dt-for-v6.14-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.14, round 1 Highlights: ---------- - MPU: - STM32MP13: - Populate all timer counter nodes in Soc file. - Enable counter (timers) on stm32mp135f-dk. - DH core: increase CPU voltage to fit with STM32MP135F datasheet. - STMP32MP15: - Populate all timer counter nodes in Soc file. - Enable counter (timers) on stm32mp15 EV1 and DK boards. - OCTAVO: - LXA-TAC (gen1/2): disable RTC, update aliases and adjust USB gadget. - Add LXA-TAC gen3 based on OSD32MP153x SIP: STMP32MP153, RAM, PMIC. - DH: minor fixes. - STM32MP25: - Enable imx335/CSI/DCMIPP pipeline on stm32mp257f-ev1. - Add I2S, SAI, SPDIFRX supports. - Add and enable COMBOPHY on stm32mp257f-ev1. Combophy is used by PCIe and USB3. * tag 'stm32-dt-for-v6.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (23 commits) arm64: dts: st: enable imx335/csi/dcmipp pipeline on stm32mp257f-ev1 arm64: dts: st: add csi & dcmipp node in stm32mp25 ARM: dts: stm32: Swap USART3 and UART8 alias on STM32MP15xx DHCOM SoM ARM: dts: stm32: add counter subnodes on stm32mp157 dk boards ARM: dts: stm32: add counter subnodes on stm32mp157c-ev1 ARM: dts: stm32: add counter subnodes on stm32mp135f-dk ARM: dts: stm32: populate all timer counter nodes on stm32mp15 ARM: dts: stm32: populate all timer counter nodes on stm32mp13 ARM: dts: stm32: lxa-tac: Add support for generation 3 devices ARM: dts: stm32: lxa-tac: move adc and gpio{e,g} to gen{1,2} boards dt-bindings: arm: stm32: add compatible strings for Linux Automation LXA TAC gen 3 ARM: dts: stm32: lxa-tac: adjust USB gadget fifo sizes for multi function ARM: dts: stm32: lxa-tac: extend the alias table ARM: dts: stm32: lxa-tac: disable the real time clock ARM: dts: stm32: Fix IPCC EXTI declaration on stm32mp151 ARM: dts: stm32: Sort M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT ARM: dts: stm32: Increase CPU core voltage on STM32MP13xx DHCOR SoM ARM: dts: stm32: Deduplicate serial aliases and chosen node for STM32MP15xx DHCOM SoM arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 board arm64: dts: st: Add combophy node on stm32mp251 ... Link: https://lore.kernel.org/r/7ffcca65-3953-413a-bcf3-0702a6b0518b@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-21arm64: dts: allwinner: a100: Add syscon nodesCody Eksal
The Allwinner A100 has a system configuration block, denoted as SYS_CFG in the user manual's memory map. It is undocumented in the manual, but a glance at the vendor tree shows this block is similar to its predecessors in the A64 and H6. The A100 also has 3 SRAM blocks: A1, A2, and C. Add all of these to the SoC's device tree. Reviewed-by: Parthiban Nallathambi <parthiban@linumiz.com> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> Link: https://patch.msgid.link/20241218-a100-syscon-v2-2-dae60b9ce192@epochal.quest Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-12-21dt-bindings: sram: sunxi-sram: Add A100 compatibleCody Eksal
The Allwinner A100 has a system configuration block similar to that of the A64 and H6. Add a compatible for it. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> Link: https://patch.msgid.link/20241218-a100-syscon-v2-1-dae60b9ce192@epochal.quest Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-12-20arm64: dts: st: enable imx335/csi/dcmipp pipeline on stm32mp257f-ev1Alain Volmat
Enable the camera pipeline with a imx335 sensor connected to the dcmipp via the csi interface. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20arm64: dts: st: add csi & dcmipp node in stm32mp25Alain Volmat
Add nodes describing the csi and dcmipp controllers handling the camera pipeline on the stm32mp25x. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20ARM: dts: stm32: Swap USART3 and UART8 alias on STM32MP15xx DHCOM SoMMarek Vasut
Swap USART3 and UART8 aliases on STM32MP15xx DHCOM SoM, make sure UART8 is listed first, USART3 second, because the UART8 is labeled as UART2 on the SoM pinout, while USART3 is labeled as UART3 on the SoM pinout. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20ARM: dts: stm32: add counter subnodes on stm32mp157 dk boardsFabrice Gasnier
Enable the counter nodes without dedicated pins. With such configuration, the counter interface can be used on internal clock to generate events. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20ARM: dts: stm32: add counter subnodes on stm32mp157c-ev1Fabrice Gasnier
Enable the counter nodes without dedicated pins. With such configuration, the counter interface can be used on internal clock to generate events. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20ARM: dts: stm32: add counter subnodes on stm32mp135f-dkFabrice Gasnier
Enable the counter nodes without dedicated pins. With such configuration, the counter interface can be used on internal clock to generate events. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20ARM: dts: stm32: populate all timer counter nodes on stm32mp15Fabrice Gasnier
Counter driver originally had support limited to quadrature interface and simple counter. It has been improved[1], so add the remaining stm32 timer counter nodes. [1] https://lore.kernel.org/linux-arm-kernel/20240307133306.383045-1-fabrice.gasnier@foss.st.com/ Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20ARM: dts: stm32: populate all timer counter nodes on stm32mp13Fabrice Gasnier
Counter driver originally had support limited to quadrature interface and simple counter. It has been improved[1], so add the remaining stm32 timer counter nodes. [1] https://lore.kernel.org/linux-arm-kernel/20240307133306.383045-1-fabrice.gasnier@foss.st.com/ Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-19arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie1Nícolas F. R. A. Prado
The MAC reset for PCIe port 1 on MT8195 when asserted during suspend causes the system to hang during resume with the following error (with no_console_suspend enabled): mtk-pcie-gen3 112f8000.pcie: PCIe link down, current LTSSM state: detect.quiet (0x0) mtk-pcie-gen3 112f8000.pcie: PM: dpm_run_callback(): genpd_resume_noirq+0x0/0x24 returns -110 mtk-pcie-gen3 112f8000.pcie: PM: failed to resume noirq: error -110 This issue is specific to MT8195. On MT8192 with the PCIe reset, MT8192_INFRA_RST4_PCIE_TOP_SWRST, added to the DT node, the issue is not observed. Since without the reset, the PCIe controller and WiFi card connected to it, work just as well, remove the reset to allow the system to suspend and resume properly. Fixes: ecc0af6a3fe6 ("arm64: dts: mt8195: Add pcie and pcie phy nodes") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20241218-mt8195-pcie1-reset-suspend-fix-v1-1-1c021dda42a6@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-19arm64: dts: mt7986: add overlay for SATA power socket on BPI-R3Frank Wunderlich
Bananapi R3 has a Power socket entended for using external SATA drives. This Socket is off by default but can be switched with gpio 8. Add an overlay to activate it. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20241206132401.70259-1-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-19arm64: dts: mediatek: mt8188: Add GPU speed bin NVMEM cellsHsin-Te Yuan
On the MT8188, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse. Add the NVMEM cell, and tie it to the GPU. Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Link: https://lore.kernel.org/r/20241213-speedbin-v1-1-a0053ead9477@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-19arm64: dts: mediatek: mt8183: willow: Support second source touchscreenHsin-Te Yuan
Some willow devices use second source touchscreen. Fixes: f006bcf1c972 ("arm64: dts: mt8183: Add kukui-jacuzzi-willow board") Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Link: https://lore.kernel.org/r/20241213-touchscreen-v3-2-7c1f670913f9@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-19arm64: dts: mediatek: mt8183: kenzo: Support second source touchscreenHsin-Te Yuan
Some kenzo devices use second source touchscreen. Fixes: 0a9cefe21aec ("arm64: dts: mt8183: Add kukui-jacuzzi-kenzo board") Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Link: https://lore.kernel.org/r/20241213-touchscreen-v3-1-7c1f670913f9@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-17arm64: dts: bcm4908: nvmem-layout conversionRosen Penev
nvmem-layout is a more flexible replacement for nvmem-cells. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://lore.kernel.org/r/20241203233632.184861-1-rosenp@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: bcmbca: bcm4908: Add DT for Zyxel EX3510-BSam Edwards
Zyxel EX3510-B is a WiFi 6 capable home gateway (family) based on the BCM4906 SoC, with 512MiB of RAM and 512MiB of NAND flash. WiFi support consists of a BCM6710 and a BCM6715 attached to separate PCIe buses. Add an initial devicetree for this system, with support for: - Onboard UART (per base dtsi) - USB (2.0 only; superspeed devices are treated as high-speed due to an unknown cause) - Both buttons (rear reset, front WPS) - Almost all LEDs: - Power (red/green) - Internet (red/green) - WAN (green) - LAN (green; anode is connected to GPIO 13 so currently nonfunctioning) - USB (green) - WPS button (red/green) - Absent in DT: There are 2.4GHz/5.0GHz WiFi status LEDs connected to the WiFi chips instead of the SoC. - NAND flash - Embedded Ethernet switch - Factory-programmed Ethernet MAC address WiFi cannot be enabled at this time due to Linux lacking drivers for both the PCIe controllers and the PCIe WiFi peripherals. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20241009215454.1449508-3-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17dt-bindings: arm64: bcmbca: Add Zyxel EX3510-B based on BCM4906Sam Edwards
This is a series (EX3510-B0 and EX3510-B1) of residential gateways based on BCM4906, a stripped-down version of the BCM4908 SoC. Although Zyxel's marketing materials call this a "series," the EX3510-B1 appears to be a very minor revision of the EX3510-B0, with only changes that are transparent to software. As far as Linux is concerned, this "series" effectively represents a single model. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241009215454.1449508-2-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: bcmbca: bcm4908: Protect cpu-release-addrSam Edwards
The `cpu-release-addr` property is relevant only when the "spin-table" enable method is used. It is the physical address where the bootloader expects Linux to write the secondary CPU entry point's physical address. On this platform, only the CFE bootloader uses this method: U-Boot uses PSCI instead. CFE actually walks the FDT to learn this address, so we're free to put it wherever we want. We only need to make sure that it goes in a reserved-memory block so that writing to it during early boot does not risk conflicting with an unrelated memory allocation: this was not done. Since the previous patch reserved the first page of memory for CFE's secondary-CPU init stub, which is actually much smaller than a page, just put this address at the end of that page and it shall be so protected. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20241005050155.61103-3-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: bcmbca: bcm4908: Reserve CFE stub areaSam Edwards
The CFE bootloader places a stub program in the first page of physical memory to hold the secondary CPUs until the boot CPU writes the release address, but does not splice a /reserved-memory node into the FDT to protect it. If Linux overwrites this program before execution reaches smp_prepare_cpus(), the secondary CPUs may become inaccessible. This is only a problem with CFE, and then only until the secondary CPUs are brought online. Ideally, there would be some hypothetical mechanism we could use to indicate that this area of memory is sensitive only during boot. But as there is none, and since it is such a small amount of memory, it is easiest to reserve it unconditionally. Therefore, add a /reserved-memory node to bcm4908.dtsi to protect the first 4KiB of physical memory. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20241005050155.61103-2-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Remove unused and undocumented propertiesRob Herring (Arm)
Remove properties which are both unused in the kernel and undocumented. Most likely they are leftovers from downstream. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241115193854.3624123-1-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Add DT for D-step version of BCM2712Dave Stevenson
The D-Step has some minor variations in the hardware, so needs matching changes to DT. Add a new DTS file that modifies the existing (C-step) devicetree. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-36-35efa83c8fc0@raspberrypi.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Add display pipeline support to BCM2712Dave Stevenson
Adds the HVS and associated hardware blocks to support the HDMI and writeback connectors on BCM2712 / Pi5. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-35-35efa83c8fc0@raspberrypi.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Add firmware clocks and power nodes to Pi5 DTDave Stevenson
BCM2712 still uses the firmware clocks and power drivers, so add them to the base device tree. The brcm,bcm2836-l1-intc controller isn't used on this platform. It is used on 32-bit kernels for the smp_boot_secondary hook, but BCM2712 can't run a 32-bit kernel. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-34-35efa83c8fc0@raspberrypi.com Link: https://lore.kernel.org/r/20241212-dt-bcm2712-fixes-v3-7-44a7f3390331@raspberrypi.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17ARM: dts: meraki-mr26: set mac address for gmac0Rosen Penev
Currently this needs to be done in userspace. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://lore.kernel.org/r/20241021015147.172700-1-rosenp@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17ARM: dts: broadcom: Add Genexis XG6846B DTS fileLinus Walleij
This adds a device tree for the Genexis XG6846B router. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-9-8375a0e1f89f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17dt-bindings: arm: bcmbca: Add Genexis XG6846BLinus Walleij
This adds the device tree bindings for the Genexis XG6846B router/gateway/broadband modem. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-8-8375a0e1f89f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17dt-bindings: vendor-prefixes: Add GenexisLinus Walleij
Genexis is Swedish/Dutch company producing broadband access equipment. Link: https://genexis.eu/ Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-7-8375a0e1f89f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17ARM: dts: bcm6846: Add ARM PL081 DMA blockLinus Walleij
The ARM PL081 DMA controller can be found in the BCM6846 memory map, and it turns out to work. The block may be used as DMA engine for some of the peripherals (maybe the EMMC controller found in the same group of peripherals?) but it can always be used as a memcpy engine, which is a generic "blitter". I tested it with the dmatest module, and it copies lots of data very fast and fires hundreds of thousands of interrupts so it works just fine. Add it to the BCM6846 DTSI file. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-6-8375a0e1f89f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17ARM: dts: bcm6846: Add LED controllerLinus Walleij
Add the BCMBCA LED controller to the BCM6846 DTSI. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-5-8375a0e1f89f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 11:13:02 +0000