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2024-02-06arm64: dts: qcom: x1e80100: Add TCSR nodeAbel Vesa
Add the TCSR clock controller and register space node. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-5-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodesSibi Sankar
Add ADSP and CDSP remoteproc nodes on X1E80100 platforms. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-4-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: x1e80100: Add QMP AOSS nodeSibi Sankar
Add a node for the QMP AOSS. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-3-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: x1e80100: Add SMP2P nodesSibi Sankar
SMP2P is used for interrupting and being interrupted about remoteproc state changes related to the audio, compute and sensor subsystems. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-2-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: x1e80100: Add IPCC nodeSibi Sankar
Add the IPCC node, used to send and receive IPC signals with remoteprocs. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-1-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06Merge branch ↵Bjorn Andersson
'20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into arm64-for-6.9 Merge the X1E clock binding topic branch, to gain access to the many clock defines.
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Camera Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Camera Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock ControllerAbel Vesa
Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-4-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 GPU Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Graphics Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-3-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Display Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-2-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: Drop the SM8650 DISPCC dedicated schemaAbel Vesa
The block is the same between these platforms, at least from devicetree point of view. So drop the dedicated schema and use the SM8550 one instead. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-1-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sa8775p: Add new memory map updates to SA8775PNinad Naik
New memory map layout changes (by Qualcomm firmware) have brought in updates to base addresses and/or size for different memory regions like cpcucp_fw, tz-stat, and also introduces new memory regions for resource manager firmware. The updated memory map also fixes existing issues pertaining to boot up failure while running memtest, thus improving stability. This change brings in these corresponding memory map updates to the device tree for SA8775P SoC platform, which currently is in its development stage. Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com> Tested-by: Eric Chanudet <echanude@redhat.com> # sa8775p-ride Link: https://lore.kernel.org/r/20240125055134.7015-1-quic_ninanaik@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02arm64: dts: qcom: qcm6490-idp: Include PM7250BUmang Chheda
Include PM7250B PMIC for qcm6490-idp. Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240125115300.3496783-1-quic_uchheda@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1Neil Armstrong
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs received from endpoint devices to the CPU using GIC-ITS MSI controller. Add support for it. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. Like SM8450 & SM8550, the IDs are swapped, but works fine on PCIe0 and PCIe1. WiFi PCIe Device on SM8650-QRD using GIC-ITS: 159: 0 0 0 0 0 0 0 0 ITS-MSI 0 Edge PCIe PME, aerdrv 167: 0 4 0 0 0 0 0 0 ITS-MSI 524288 Edge bhi 168: 0 0 4 0 0 0 0 0 ITS-MSI 524289 Edge mhi 169: 0 0 0 34 0 0 0 0 ITS-MSI 524290 Edge mhi 170: 0 0 0 0 3 0 0 0 ITS-MSI 524291 Edge ce0 171: 0 0 0 0 0 2 0 0 ITS-MSI 524292 Edge ce1 172: 0 0 0 0 0 0 806 0 ITS-MSI 524293 Edge ce2 173: 0 0 0 0 0 0 0 76 ITS-MSI 524294 Edge ce3 174: 0 0 0 0 0 0 0 0 ITS-MSI 524295 Edge ce5 175: 0 13 0 0 0 0 0 0 ITS-MSI 524296 Edge DP_EXT_IRQ 176: 0 0 0 0 0 0 0 0 ITS-MSI 524297 Edge DP_EXT_IRQ 177: 0 0 0 5493 0 0 0 0 ITS-MSI 524298 Edge DP_EXT_IRQ 178: 0 0 0 0 82 0 0 0 ITS-MSI 524299 Edge DP_EXT_IRQ 179: 0 0 0 0 0 7204 0 0 ITS-MSI 524300 Edge DP_EXT_IRQ 180: 0 0 0 0 0 0 672 0 ITS-MSI 524301 Edge DP_EXT_IRQ 181: 0 0 0 0 0 0 0 30 ITS-MSI 524302 Edge DP_EXT_IRQ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-pcie-its-v1-1-cb506deeb43e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02arm64: dts: qcom: qcm6490-idp: Add definition for three LEDsHui Liu
Add definition for three LEDs to make sure they can be enabled base on QCOM LPG LED driver. Signed-off-by: Hui Liu <quic_huliu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-lpg-v6-1-f879cecbce69@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02arm64: dts: qcom: sm8650-qrd: add USB-C Altmode SupportNeil Armstrong
Add the necessary nodes to support the USB-C Altmode path by adding the following - WCD939x USBSS Mux I2C device - nb7vpq904m Redriver I2C device - Port/Endpoint graph links bettween PMIC-Glink, Mux, Redriver and USB PHY nodes. WCD939x USBSS port 2 Path to Codec will be added later when Audio support is added. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240123-topic-sm8650-upstream-altmode-v3-1-300a5ac80e1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02arm64: dts: qcom: sm8550-qrd: enable TouchscreenNeil Armstrong
Add Goodix Berlin touchscreen controller node for the SM8550 QRD connected to the SPI4 controller. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240131-topic-sm8550-upstream-qrd8550-touch-v1-1-007f61158aa8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: Add support for Xiaomi Redmi Note 9SJoe Mason
Add a device tree for the Xiaomi Redmi Note 9S (curtana) phone, based on sm7125-xiaomi-common.dtsi. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Joe Mason <buddyjojo06@outlook.com> Signed-off-by: David Wronek <davidwronek@gmail.com> Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-8-f7d1212c8ebb@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sm7125-xiaomi-common: Add UFS nodesDavid Wronek
Enable the UFS found on the SM7125 Xiaomi smartphones. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: David Wronek <davidwronek@gmail.com> Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-7-f7d1212c8ebb@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sc7180: Add UFS nodesDavid Wronek
Add the UFS, QMP PHY and ICE nodes for the Qualcomm SC7180 SoC. Signed-off-by: David Wronek <davidwronek@gmail.com> Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-6-f7d1212c8ebb@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30dt-bindings: arm: qcom: Add Xiaomi Redmi Note 9SDavid Wronek
Document the Xiaomi Redmi Note 9S (curtana) smartphone, which is based on the Qualcomm SM7125 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Wronek <davidwronek@gmail.com> Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-4-f7d1212c8ebb@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sda660-ifc6560: enable USB 3.0 PHYDmitry Baryshkov
The Inforce IFC6560 board actually has USB SS lines routed to the USB-C connector. Enable USB 3.0 PHY and SS mode for the USB3 host. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-4-2fbd683aea77@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sdm630: add USB QMP PHY supportDmitry Baryshkov
Define USB3 QMP PHY presend on the SDM630 / SDM660 platforms. Enable it by default in the USB3 host, but (for compatibility), force USB 2.0 mode for all defined boards. The boards should opt-in to enable USB 3.0 support. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-3-2fbd683aea77@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definitionBryan O'Donoghue
Add CAMSS block definition for sc8280xp. This drop contains definitions for the following components on sc8280xp: VFE * 4 VFE Lite * 4 CSID * 4 CSIPHY * 4 This dtsi definition has been developed and validated on a Lenovo X13s laptop. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-4-cdd5c57ff1dc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sc8280xp: camss: Add CCI definitionsBryan O'Donoghue
sc8280xp has four Camera Control Interface (CCI) blocks which pinout to two I2C master controllers for each CCI. The CCI I2C pins are not muxed so we define them in the dtsi. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-3-cdd5c57ff1dc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sa8295p-adp: Enable GPUBjorn Andersson
With the necessary support in place for supplying VDD_GFX from the MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU and the GPU on the SA8295P ADP. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-7-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sa8295p-adp: add max20411Bjorn Andersson
The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the bus. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-6-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpuccBjorn Andersson
The SA8295P and SA8540P uses an external regulator (max20411), and gfx.lvl is not provided by rpmh. Drop the power-domains property of the gpucc node to reflect this. Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-5-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: sm7225-fairphone-fp4: Switch firmware ext to .mbnLuca Weiss
Specify the file name for the squashed/non-split firmware with the .mbn extension instead of the split .mdt. The kernel can load both but the squashed version is preferred in dts nowadays. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240110-fp4-mbn-v1-1-45e7e33b1834@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: rename PM2250 to PM4125Dmitry Baryshkov
It seems, the only actual mentions of PM2250 can be found are related to the Qualcomm RB1 platform. However even RB1 schematics use PM4125 as a PMIC name. Rename PM2250 to PM4125 to follow the documentation. Note, this doesn't change the compatible strings. There was a previous argument regarding renaming of compat strings. Fixes: c309b9a54039 ("arm64: dts: qcom: Add initial PM2250 device tree") Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240128-pm2250-pm4125-rename-v2-2-d51987e9f83a@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINKLuca Weiss
Via the PMIC GLINK driver we can get info about fuel gauge, charger and USB connector events. Add the node to the dts and configure USB so that role switching works. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20231220-fp5-pmic-glink-v1-3-2a1f8e3c661c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: sdm845-oneplus-common: improve DAI node namingDavid Heidelberg
Make it easier to understand what the reg in those nodes is by using the constants provided by qcom,q6dsp-lpass-ports.h. Name nodes according to dt-binding expectations. Fix for ``` arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb: service@4: dais: Unevaluated properties are not allowed ('qi2s@22', 'qi2s@23' were unexpected) ``` Fixes: b7b734286856 ("arm64: dts: qcom: sdm845-oneplus-*: add audio devices") Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231229200245.259689-1-david@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memoryLuca Weiss
It seems we also need to reserve a region of 81 MiB called "removed_mem" otherwise we can easily hit the following error with higher RAM usage: [ 1467.809274] Internal error: synchronous external abort: 0000000096000010 [#2] SMP Fixes: eee9602ad649 ("arm64: dts: qcom: qcm6490: Add device-tree for Fairphone 5") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231229-fp5-reserved-mem-v1-1-87bb818f1397@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: sc7280: Add static properties to cryptobamLuca Weiss
When the properties num-channels & qcom,num-ees are not specified, the driver tries to read the values from registers, but this read fails and resets the device if the interconnect from the qcom,qce node is not already active when that happens. Add the static properties to not touch any registers during probe, the rest of the time when the BAM is used by QCE then the interconnect will be active already. Fixes: d488f903a860 ("arm64: dts: qcom: sc7280: add QCrypto nodes") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231229-sc7280-cryptobam-fixup-v1-1-bd8f68589b80@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: sa8775p: enable safety IRQSuraj Jaiswal
Add changes to support safety IRQ handling support for ethernet. Signed-off-by: Suraj Jaiswal <quic_jsuraj@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240110111649.2256450-3-quic_jsuraj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: apq8016-sbc-d3-camera: Use more generic node namesStephan Gerhold
Add "regulator" to the node names of the fixed regulators, and drop the "_rear" part of the camera node name since it is not part of the class of the device (which is simply "camera"). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230922-apq8016-sbc-camera-dtso-v1-1-ce9451895ca1@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: split PCIe interrupt-names entries per linesKrzysztof Kozlowski
Other PCIe nodes in SM8250 and SM8350 have one interrupt name per line, so adjust PCIe0 to match the style. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-7-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8650: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-6-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8550: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-5-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-4-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8350: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-3-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8250: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom: sm8250: provide additional MSI interrupts"). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-2-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8150: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-1-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450: Add missing interconnects to serialKonrad Dybcio
The serial ports did not have their interconnect paths specified when they were first introduced. Fix that. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Fixes: f5837418479a ("arm64: dts: qcom: sm8450: add uart20 node") Reported-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Georgi Djakov <djakov@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240116-topic-8450serial-v1-1-b685e6a5ad78@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27dt-bindings: qcom: Document new msm8916-samsung devicesRaymond Hackley
Document the new following device tree bindings used in their device trees: - samsung,fortuna3g - samsung,gprimeltecan - samsung,grandprimelte - samsung,rossa Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240120095715.13689-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphonesKrzysztof Kozlowski
Due to lack of documentation the AMIC4 and AMIC5 analogue microphones were never actually working, so the audio routing for them was added hoping it is correct. It turned out not correct - their routing should point to SWR_INPUT0 (so audio mixer TX SMIC MUX0 = SWR_MIC0) and SWR_INPUT1 (so audio mixer TX SMIC MUX0 = SWR_MIC1), respectively. With proper mixer settings and fixed LPASS TX macr codec TX SMIC MUXn widgets, this makes all microphones working on HDK8450. Cc: stable@vger.kernel.org Fixes: f20cf2bc3f77 ("arm64: dts: qcom: sm8450-hdk: add other analogue microphones") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240124121855.162730-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8150: add necessary ref clock to PCIeKrzysztof Kozlowski
The PCIe nodes should get the ref clock, according to information from Qualcomm. Link: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208105155.36097-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sdm630: Hook up GPU cooling deviceKonrad Dybcio
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-12-fda30c57e353@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8550: Hook up GPU cooling deviceKonrad Dybcio
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, unify the naming scheme of the thermal zones across the tree while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-11-fda30c57e353@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450: Hook up GPU cooling deviceKonrad Dybcio
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-10-fda30c57e353@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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