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2019-06-21drm/amd/powerplay: add helper function of smu_set_hard_freq_rangeKevin Wang
add this function to get dpm clock information. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function of smu_set_soft_freq_rangeKevin Wang
add this helper function to get dpm clk information. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function of smu_get_dpm_freq_rangeKevin Wang
add this helper function to get dpm clk information (min, max); Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function print_clk_levels for navi10Kevin Wang
add sysfs interface of print_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function to get dpm freq informationsKevin Wang
this function can help driver to get ppclk informations Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function get current clock freq interface for navi10Kevin Wang
add function of get_current_clk_freq_by_table for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resumeJack Xiao
CSIB BO is required to be pinned down to guarantee bo is always valid when resume, and to be unpinned it so that its content can be saved during suspend. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactiveJack Xiao
The following KIQ ring test could guarantee the previous unmap has been done. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: RLC must be disabled after SMU when S3 on naviJack Xiao
SMU requires to interact with RLC when disable all features, so RLC shouldn't be disabled ahead of SMU. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabledJack Xiao
MP1 cannot access clock IP during MP1 FW reload, disable PLL shutdown as a workaround. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: disable uclk dpm by defaulttiancyin
[why] The uclk dpm feature is not supported by some certain navi10 board like 18202, while supported by some board like 18201. It causes modprobe failure on 18202 board. [how] Disabled this feature by default, it can be enabled by module parameter uclk_dpm_support=1. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/VCN2.0: remove powergating for UVDW tileLeo Liu
No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21amd/powerplay: enable uclk dpmKenneth Feng
Enable uclk dpm on navi10 as the result of removing fast switch setting. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21amd/powerplay: fix the issue of uclk dpmKenneth Feng
PPSMC_MSG_SetUclkFastSwitch message can be applied on vega20, but can't on navi10. This is the prerequisite of uclk dpm on navi10. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring is ↵Xiaojie Yuan
disabled gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is enabled, so should gfx_v10_0_kiq_disable_kgq(). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: drop redundant se/sh selectionXiaojie Yuan
we already selected se/sh at the beginning of the for loop Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: enable mes FW backdoor loadingJack Xiao
It enables MES FW backdoor loading in ip block functions. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement mes enablement functionJack Xiao
After MES firmware gets loaded, it enables MES engine starting execution. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement MES firmware backdoor loadingJack Xiao
It implements MES firmware backdoor loading. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement ucode buffers destructionJack Xiao
Free ucode GPU buffers. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: upload mes data ucode to gpu bufferJack Xiao
Allocate GPU buffer and upload mes data ucode to the buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: upload mes ucode to gpu bufferJack Xiao
Allocate GPU buffer and upload ucode firmware to the buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement ucode CPU buffer destructionJack Xiao
It implements the CPU buffer destruction of ucode. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: load mes firmware file to CPU bufferJack Xiao
It requests MES firmware binary and uploads to CPU buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: add mes firmware info fieldsJack Xiao
The newly added fields is to store mes firmware related information. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/ucode: add mes firmware file supportJack Xiao
The newly added firmware struct is for mes firmware file. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/ucode: add the definitions of MES ucode and ucode dataJack Xiao
MES requires two seperate firmwares: ucode and ucode data. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma5: incorrect variable type for gpu addressJack Xiao
Incorrect programming with 64bit gpu address assignment for 32bit variable. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples testtiancyin
[why] When page fault happens, it could lead to sdma hang is RESP_MODE = 0 for non-PRT case. [how] Setting SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)Hawking Zhang
It's not needed for navi. v2: remove unused variable (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/nv: set vcn pg flagJack Xiao
Enable VCN power gating by default. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable vcn dpm scheme for naviJack Xiao
On navi1x, vcn dpm scheme was merged into powergating scheme. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/vcn2: don't access register when power gatedJack Xiao
It will cause bus hang to access register UVD_STATUS when VCN is in the state of power gated. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add new interface for vcn powergatingKenneth Feng
add new interface for vcn powrergating and vcn dpm as well. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: enable vcn powergating v2Kenneth Feng
enable vcn powergating in driver for navi10 v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/vcn2: notify SMU power up/down VCNJack Xiao
For sw control power gating, it needs notify SMU to power up/down VCN when enter/exit working state. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: fix issues for suspend/resumeJack Xiao
1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement. 2). Need wait for unmapping queue done before continue execution. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpmHuang Rui
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm doesn't work so far and we needs to enable the sysfs interfaces. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: update smu11_driver_if_navi10.hKenneth Feng
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.15.0 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: fix resume failure when enabling async gfx ringXiaojie Yuan
'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue() Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: disable some gfx light sleepTianci Yin
temporarily disable to avoid s3 test failure. s3 test failure log: "[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=8278, emitted seq=8281" Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: update gfx golden settingsTianci Yin
add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and mmGL2C_CGTT_SCLK_CTRL. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workableHuang Rui
This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: fix the incorrect type of pptableKenneth Feng
This patch is to fix the incorrect type of pptable, otherwise, the data will be totally wrong in parsing phase. Signed-off-by: Kenneth Feng <Kenneth.Feng@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2)Huang Rui
This header is actually for each asic, so we should not include in smu_v11_0.c. And rename the one for navi10. v2: add hack for XGMI (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: move getting MAX_FAN_RPM value to asic levelHuang Rui
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to asic level. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: introduce smu power source type to handle AC/DC source ↵Huang Rui
for each asic This patch introduces new smu power source type, it's to handle the different AC/DC source defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: move Watermarks_t uses into asic levelHuang Rui
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: move SmuMetrics_t uses into asic levelHuang Rui
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: move PPTable_t uses into asic levelHuang Rui
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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