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2021-09-30drm/i915: Pimp HSW+ transcoder state readoutVille Syrjälä
Adjust the HSW+ transcoder state readout to just read through all the possible transcoders for the pipe, and stuff the results in a bitmask. We can conveniently cross check the bitmask for invalid combinations of enabled transcoders, and later we can easily extend the bitmask readout to handle the bigjoiner case. One slight change in behaviour is that we no longer read out the AONOFF->force_pfit.pfit bit for all the enabled "panel transcoders". But having more than one enabled would anyway be illegal so no big loss. Also the AONOFF selection should only ever be used on HSW, which only has the EDP transcoder an no DSI transcoders. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210913144440.23008-10-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2021-09-30drm/i915/fbc: Allow FBC with Yf tilingVille Syrjälä
FBC+Yf tiling seems to work just fine, and unlike with linear the hardware does appear to correctly calculate the CFB stride with using the override stride on both cfl and glk. So no need for any additional tweaks. Cc: Uma Shankar <uma.shankar@intel.com> #v2 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210924141330.1515-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2021-09-30drm/i915: Enable TPS3/4 on all platforms that support themVille Syrjälä
Stop using HBR2/3 support as a proxy for TPS3/4 support. The two are no longer 1:1 in the hardware, arguably they never were due to HSW ULX which does support TPS3 while being limited to HBR1. In more recent times GLK gained support for TPS4 while being limited to HBR2. And on CNL+ some ports support HBR3 while others are limited to HBR2, but all ports support TPS4. v2: s/INTEL_GEN/DISPLAY_VER/ Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929162404.6717-1-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2021-09-30drm/i915: Drop pointless fixed_mode checks from dsi codeVille Syrjälä
We don't support dsi displays without a fixed mode, so drop all the pointless checks. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210923200109.4459-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-09-30drm/i915: Reject user modes that don't match fixed mode's refresh rateVille Syrjälä
When using a panel with a fixed mode we don't change the refresh rate of the display. Reject any user requested mode which doesn't match that fixed refresh rate. Unfortunately when Xorg sees the scaling_mode property on the connecor it likes to automagically cook up modes whose refresh rate is a fair bit off from the fixed refresh rate we use. So we have to give it some extra latitude so that we don't start to reject all of it. v2: sDVO now uses intel_panel_compute_config() too v3: Add a debug message to inform the user what happened References: https://gitlab.freedesktop.org/drm/intel/-/issues/2939 References: https://gitlab.freedesktop.org/drm/intel/-/issues/3969 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929184536.8332-1-ville.syrjala@linux.intel.com
2021-09-30drm/i915: Introduce intel_panel_compute_config()Ville Syrjälä
Let's introduce a compute_config() helper for fixed mode panels. For now all it does is the fixed_mode->adjusted_mode copy. Note that with sDVO we have to ask the external encoder chip to spit out our actual display timings for us, so the fixed_mode to adjusted_mode copy done by intel_panel_compute_config() is redundant, but we still want to use it to do other checks for us later. We'll be fine so long as we only call it before intel_sdvo_get_preferred_input_mode() overwrites adjusted_mode with the timings from the encoder. v2: Use intel_panel_compute_config() with sDVO Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927185207.13620-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-09-30drm/i915: Reject modes that don't match fixed_mode vrefreshVille Syrjälä
When using a fixed mode we won't change the refresh rate ever. So filter out all modes that don't match the fixed_mode's refresh rate. I'm going to declare the "rounded to nearest Hz refresh rates must match" approach good enough for now. Note that we could start supporting multiple refresh rates with panels that can do it, but that would mean replacing the single fixed mode concept with a list of fixed modes. Then we could look for the closest match to the user's requested refresh rate and use that. But all of that would be a fair bit of work so we'll leave it for later. References: https://gitlab.freedesktop.org/drm/intel/-/issues/2939 References: https://gitlab.freedesktop.org/drm/intel/-/issues/3969 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210923200109.4459-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-09-30drm/i915: Use intel_panel_mode_valid() for DSI/LVDS/(s)DVOVille Syrjälä
All fixed mode panels should behave the same way when it comes to mode filtering. Reuse the intel_panel_mode_valid() for all of them. This changes the behaviour to match what we do for eDP, ie. reject anything that doesn't exactly match the fixed mode dimensions. Users can still manually provide different sized modes which will be handled by the panel fitter just as before. The difference is that we can no longer report funny modes in the connector's mode list. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210923200109.4459-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-09-30drm/i915: Extract intel_panel_mode_valid()Ville Syrjälä
Extract intel_panel_mode_valid() from the eDP code to a generic helper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210923200109.4459-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-09-29drm/amdgpu: add cyan_skillfish asic header filesZhan Liu
This patch is to add cyan_skillfish asic header files. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Jun Lei <jun.lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amdgpu: Add a UAPI flag for hot plug/unplugAndrey Grodzovsky
To support libdrm tests. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amdgpu: drm/amdgpu: Handle IOMMU enabled caseAndrey Grodzovsky
Handle all DMA IOMMU group related dependencies before the group is removed and we try to access it after free. v2: Move the actul handling function to TTM Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/amdgpu: Validate ip discovery blobErnst Sjöstrand
We use the number_instance index that we get from the fw discovery blob to index into an array for example. Update error messages (Alex) Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29gpu: amd: replace open-coded offsetof() with builtinArnd Bergmann
The two AMD drivers have their own custom offsetof() implementation that now triggers a warning with recent versions of clang: drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer subtraction with a null pointer has undefined behavior [-Werror,-Wnull-pointer-subtraction] Change all the instances to use the normal offsetof() provided by the kernel that does not have this problem. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amdkfd: fix resource_size.cocci warningsYang Li
Use resource_size function on resource object instead of explicit computation. Clean up coccicheck warning: ./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:905:10-13: ERROR: Missing resource_size with res Reported-by: Abaci Robot <abaci@linux.alibaba.com> Reviewed-by: Amos Kong <kongjianjun@gmail.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amdgpu: fix warning for overflow checkArnd Bergmann
The overflow check in amdgpu_bo_list_create() causes a warning with clang-14 on 64-bit architectures, since the limit can never be exceeded. drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of comparison of constant 256204778801521549 with expression of type 'unsigned int' is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list)) ~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The check remains useful for 32-bit architectures, so just avoid the warning by using size_t as the type for the count. Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the list") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amdgpu: check tiling flags when creating FB on GFX8-Simon Ser
On GFX9+, format modifiers are always enabled and ensure the frame-buffers can be scanned out at ADDFB2 time. On GFX8-, format modifiers are not supported and no other check is performed. This means ADDFB2 IOCTLs will succeed even if the tiling isn't supported for scan-out, and will result in garbage displayed on screen [1]. Fix this by adding a check for tiling flags for GFX8 and older. The check is taken from radeonsi in Mesa (see how is_displayable is populated in gfx6_compute_surface). Changes in v2: use drm_WARN_ONCE instead of drm_WARN (Michel) [1]: https://github.com/swaywm/wlroots/issues/3185 Signed-off-by: Simon Ser <contact@emersion.fr> Acked-by: Michel Dänzer <mdaenzer@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/amdgpu: Add missing mp_11_0_8_sh_mask.h headerTom St Denis
The commit 2766534b766e1b12e0fa0a4e2e26929e808fde71 added the offset header but didn't add the masks. This adds the masks based on what was selected for the offsets. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/display: Pass PCI deviceid into DCCharlene Liu
[why] pci deviceid not passed to dal dc, without proper break, dcn2.x falls into dcn3.x code path [how] pass in pci deviceid, and break once dal_version initialized. Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/display: Update VCP X.Y logging to improve usefulnessGeorge Shen
[Why] Recently debugging efforts have involved setting/checking the X.Y value used during payload allocation. Current output for Y was calculated with incorrect bitshift. Y value is also not human readable. [How] Refactor logging into separate function. Fix Y calculation error and format output to be human readable. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/display: Handle Y carry-over in VCP X.Y calculationGeorge Shen
[Why/How] Theoretically rare corner case where ceil(Y) results in rounding up to an integer. If this happens, the 1 should be carried over to the X value. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/display: make verified link cap not exceeding max link capWenjing Liu
[why] There is a chance verified link cap can be greater than max link cap. This causes software hang because we cannot power up PHY with link rate that cannot handle. The change is to guard verfieid link cap from becoming larger than max link cap our PHy can support. Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/display: initialize backlight_ramping_override to falseJosip Pavic
[Why] Stack variable params.backlight_ramping_override is uninitialized, so it contains junk data [How] Initialize the variable to false Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/amd/display: Defer LUT memory powerdown until LUT bypass latchesMichael Strauss
[WHY] Blnd, 3dlut, and shaper LUT select registers are double buffered, however their accompanying LUT memory shutdown registers are not. As a result, shutting down LUT memory immediately after setting a block to bypass causes corruption as bypass only happens at next Vupdate. [HOW] Re-enable mem low power for CM block Force optimization on next flip and disable LUT memory during optimization sequence if LUT select field is then set to bypass v2: squash in CONFIG_DRM_AMD_DC_DCN fix (Alex) Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-29drm/i915/tc: Fix system hang on ADL-P during TypeC PHY disconnectImre Deak
The PHY ownership release->AUX PW disable steps during a modeset disable->PHY disconnect sequence can hang the system if the PHY disconnect happens after disabling the PHY's PLL. The spec doesn't require a specific order for these two steps, so this issue is still being root caused by HW/FW teams. Until that is found, let's make sure the disconnect happens before the PLL is disabled, and do this on all platforms for consistency. v2: Add a TODO comment to remove the w/a once the issue is root caused/fixed. (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-7-imre.deak@intel.com
2021-09-29drm/i915/tc: Drop extra TC cold blocking from intel_tc_port_connected()Imre Deak
After the previous patch the driver holds a power domain blocking TC-cold whenever the port is locked, so we can remove the extra blocking around the lock/unlock sequence. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-13-imre.deak@intel.com
2021-09-29drm/i915/tc: Fix TypeC PHY connect/disconnect logic on ADL-PImre Deak
So far TC-cold was blocked only for the duration of TypeC mode resets. The DP-alt and legacy modes require TC-cold to be blocked also whenever the port is in use (AUX transfers, enable modeset), and this was ensured by the held PHY ownership flag. On ADL-P this doesn't work, since the PHY ownership flag is in a register backed by the PW#2 power well. Whenever this power well is disabled the ownership flag is cleared by the HW under the driver. The only way to cleanly release and re-acquire the PHY ownership flag and also allow for power saving (by disabling the display power wells and reaching DC5/6 states) is to hold the TC-cold blocking power domains while the PHY is connected and disconnect/reconnect the PHY on-demand around AUX transfers and modeset enable/disables. Let's do that, disconnecting a PHY with a 1 sec delay after it becomes idle. For consistency do this on all platforms and TypeC modes. v2: Add tc_mode!=disconnected and phy_is_owned asserts to __intel_tc_port_lock(). Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-6-imre.deak@intel.com
2021-09-29drm/i915/icl/tc: Remove the ICL special casing during TC-cold blockingImre Deak
While a TypeC port mode is locked a DISPLAY_CORE power domain reference is held, which implies a runtime PM ref. By removing the ICL !legacy port special casing, a TC_COLD_OFF power domain reference will be taken for such ports, which also translates to a runtime PM ref on that platform. A follow-up change will stop holding the DISPLAY_CORE power domain while the port is locked. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-11-imre.deak@intel.com
2021-09-29drm/i915/tc: Avoid using legacy AUX PW in TBT modeImre Deak
For the ADL-P TBT mode the spec doesn't require blocking TC-cold by using the legacy AUX power domain. To avoid the timeouts that this would cause during PHY disconnect/reconnect sequences (which will be more frequent after a follow-up change) use the TC_COLD_OFF power domain in TBT mode on all platforms. On TGL this power domain blocks TC-cold via a PUNIT command, while on other platforms the domain just takes a runtime PM reference. If the HPD live status indicates that the port mode needs to be reset - for instance after switching from TBT to a DP-alt sink - still take the AUX domain, since the IOM firmware handshake requires this. v2: Rebased on v2 of the previous patch. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-5-imre.deak@intel.com
2021-09-29drm/i915/tc: Refactor TC-cold block/unblock helpersImre Deak
A follow-up change will select the TC-cold blocking power domain based on the TypeC mode, prepare for that here. Also bring intel_tc_cold_requires_aux_pw() earlier to its logical place for readability. No functional change. v2: Add code comment about IOM reg accesses in TCCOLD. (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-4-imre.deak@intel.com
2021-09-29drm/i915/tc: Add a mode for the TypeC PHY's disconnected stateImre Deak
A follow-up change will start to disconnect/re-connect PHYs around AUX transfers and modeset enable/disables. To prepare for that add a new TypeC PHY disconnected mode, to help tracking the TC-cold blocking power domain status (no power domain in disconnected state, mode dependent power domain in connected state). v2: Move the !disconnected mode and phy-owned asserts in __intel_tc_port_lock() later in the patchset, when the asserts will hold. (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-3-imre.deak@intel.com
2021-09-29drm/i915/tc: Don't keep legacy TypeC ports in connected state w/o a sinkImre Deak
A follow-up patch will disconnect/reconnect PHYs around AUX transfers and modeset enable/disables. To prepare for that and make things consistent for all TypeC modes stop connecting the PHY in legacy mode without a sink being connected. This was done before since in legacy mode the PHY is dedicated to display usage, so there was no point in disconnecting it. However after the follow-up changes the TC-cold blocking power domains will be held as long as the PHY is in the connected state, so we'll need to disconnect/re-connect the PHY in all TypeC modes to allow for power saving. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-7-imre.deak@intel.com
2021-09-29drm/i915/tc: Add/use helpers to retrieve TypeC port propertiesImre Deak
Instead of directly accessing the TypeC port internal struct members, add/use helpers to retrieve the corresponding properties. No functional change. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-6-imre.deak@intel.com
2021-09-29drm/i915/tc: Check for DP-alt, legacy sinks before taking PHY ownershipImre Deak
On ADL-P the PHY ready/complete flag is always set even in TBT-alt mode. To avoid taking the PHY ownership and the following spurious "PHY sudden disconnect" messages on this platform when connecting the PHY in TBT mode, check if there is any DP-alt or legacy sink connected before taking the ownership. v2: (Jose) - Fix debug message clarifying that a TBT sink can be connected. - Add comments describing the PHY complete HW flag semantic differences between adl-p and other platforms. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-2-imre.deak@intel.com
2021-09-29drm/i915/tc: Remove waiting for PHY complete during releasing ownershipImre Deak
Waiting for the PHY complete flag to clear when releasing the PHY ownership was add in commit ddec362724f9 ("drm/i915: Wait for TypeC PHY complete flag to clear in safe mode") This isn't required by the spec, the vague idea was to make the handshake with the firmware more robust, without actual evidence for when it would be needed. Checking this again, the flag doesn't clear on ICL until after the PHY's PLL is disabled and the flag is permanently set on ADL-P. To avoid the spurious timeout messages in dmesg, just remove this wait. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-4-imre.deak@intel.com
2021-09-29drm/i915/adlp/tc: Fix PHY connected check for Thunderbolt modeImre Deak
On ADL-P the PHY ready (aka status complete on other platforms) flag is always set, besides when a DP-alt, legacy sink is connected also when a TBT sink is connected or nothing is connected. So assume the PHY to be connected when both the TBT live status and PHY ready flags are set. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-3-imre.deak@intel.com
2021-09-29drm/i915/tc: Fix TypeC port init/resume time sanitizationImre Deak
Atm during driver loading and system resume TypeC ports are accessed before their HW/SW state is synced. Move the TypeC port sanitization to the encoder's sync_state hook to fix this. v2: Handle the encoder disabled case in gen11_dsi_sync_state() as well (Jose, Jani) Fixes: f9e76a6e68d3 ("drm/i915: Add an encoder hook to sanitize its state during init/resume") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-1-imre.deak@intel.com
2021-09-29drm/i915/gen11: Disable cursor clock gating in HDR modeTejas Upadhyay
Display underrun in HDR mode when cursor is enabled. RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h. As per W/A 1604331009, Disable cursor clock gating in HDR mode. Bspec : 33451 Changes since V6: - Address checkpatch warnings - Bit ordering Changes since V5: - replace intel_de_read with intel_de_rmw - Jani Changes since V4: - Added WA needed check - Ville - Replace BIT with REG_BIT - Ville - Add WA enable/disable support back which was added in V1 - Ville Changes since V3: - Disable WA when not in HDR mode or cursor plane not active - Ville - Extract required args from crtc_state - Ville - Create HDR mode API using bdw_set_pipemisc ref - Ville - Tested with HDR video as well full setmode, WA applies and disables Changes since V2: - Made it general gen11 WA - Removed WA needed check - Added cursor plane active check - Once WA enable, software will not disable Changes since V1: - Modified way CLKGATE_DIS_PSL bit 28 was modified Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929052442.2543054-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2021-09-29drm/ttm: add TTM_TT_FLAG_EXTERNAL_MAPPABLEMatthew Auld
In commit: commit 667a50db0477d47fdff01c666f5ee1ce26b5264c Author: Thomas Hellstrom <thellstrom@vmware.com> Date: Fri Jan 3 11:17:18 2014 +0100 drm/ttm: Refuse to fault (prime-) imported pages we introduced the restriction that imported pages should not be directly mappable through TTM(this also extends to userptr). In the next patch we want to introduce a shmem_tt backend, which should follow all the existing rules with TTM_PAGE_FLAG_EXTERNAL, since it will need to handle swapping itself, but with the above mapping restriction lifted. v2(Christian): - Don't OR together EXTERNAL and EXTERNAL_MAPPABLE in the definition of EXTERNAL_MAPPABLE, just leave it the caller to handle this correctly, otherwise we might encounter subtle issues. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132629.353541-3-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/ttm: add some kernel-doc for TTM_TT_FLAG_*Matthew Auld
Move it to inline kernel-doc, otherwise we can't add empty lines it seems. Also drop the kernel-doc for pages_list, which doesn't seem to exist. v2(Christian): - Add a note that FLAG_SWAPPED shouldn't need to be touched by drivers. - Mention what FLAG_POPULATED does. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132629.353541-2-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/ttm: s/FLAG_SG/FLAG_EXTERNAL/Matthew Auld
It covers more than just ttm_bo_type_sg usage, like with say dma-buf, since one other user is userptr in amdgpu, and in the future we might have some more. Hence EXTERNAL is likely a more suitable name. v2(Christian): - Rename these to TTM_TT_FLAGS_* - Fix up all the holes in the flag values Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132629.353541-1-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/ttm: remove TTM_PAGE_FLAG_NO_RETRYMatthew Auld
No longer used it seems. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927114114.152310-4-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/ttm: move ttm_tt_{add, clear}_mapping into amdgpuMatthew Auld
Now that setting page->index shouldn't be needed anymore, we are just left with setting page->mapping, and here it looks like amdgpu is the only user, where pointing the page->mapping at the dev_mapping is used to verify that the pages do indeed belong to the device, if userspace later tries to touch them. v2(Christian): - Drop the functions altogether and just inline modifying the page->mapping Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927114114.152310-3-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/ttm: stop setting page->index for the ttm_ttMatthew Auld
In commit: commit 58aa6622d32af7d2c08d45085f44c54554a16ed7 Author: Thomas Hellstrom <thellstrom@vmware.com> Date: Fri Jan 3 11:47:23 2014 +0100 drm/ttm: Correctly set page mapping and -index members we started setting the page->mapping and page->index to point to the virtual address space, if the pages were faulted with TTM. Apparently this was needed for core-mm to able to reverse lookup the virtual address given the struct page, and potentially unmap it from the page tables. However as pointed out by Thomas, since we are now using PFN_MAP, instead of say PFN_MIXED, this should no longer be the case. There was also apparently some usecase in vmwgfx which needed this for dirty tracking, but that also doesn't appear to be the case anymore, as pointed out by Thomas. We still need keep the page->mapping for now, since that is still needed for different reasons, but we try to address that in the next patch. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927114114.152310-2-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/ttm: stop calling tt_swapin in vm_accessMatthew Auld
In commit: commit 09ac4fcb3f255e9225967c75f5893325c116cdbe Author: Felix Kuehling <Felix.Kuehling@amd.com> Date: Thu Jul 13 17:01:16 2017 -0400 drm/ttm: Implement vm_operations_struct.access v2 we added the vm_access hook, where we also directly call tt_swapin for some reason. If something is swapped-out then the ttm_tt must also be unpopulated, and since access_kmap should also call tt_populate, if needed, then swapping-in will already be handled there. If anything, calling tt_swapin directly here would likely always fail since the tt->pages won't yet be populated, or worse since the tt->pages array is never actually cleared in unpopulate this might lead to a nasty uaf. Fixes: 09ac4fcb3f25 ("drm/ttm: Implement vm_operations_struct.access v2") Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927114114.152310-1-matthew.auld@intel.com Signed-off-by: Christian König <christian.koenig@amd.com>
2021-09-29drm/i915: Fix runtime pm handling in i915_gem_shrinkMaarten Lankhorst
We forgot to call intel_runtime_pm_put on error, fix it! Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: cf41a8f1dc1e ("drm/i915: Finally remove obj->mm.lock.") Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: <stable@vger.kernel.org> # v5.13+ Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210830121006.2978297-9-maarten.lankhorst@linux.intel.com
2021-09-29drm/virtio: implement context init: advertise feature to userspaceGurchetan Singh
This advertises the context init feature to userspace, along with a mask of supported capabilities. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Acked-by: Lingfeng Yang <lfy@google.com> Link: http://patchwork.freedesktop.org/patch/msgid/20210921232024.817-13-gurchetansingh@chromium.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-09-29drm/virtio: implement context init: add virtio_gpu_fence_eventGurchetan Singh
Similar to DRM_VMW_EVENT_FENCE_SIGNALED. Sends a pollable event to the DRM file descriptor when a fence on a specific ring is signaled. One difference is the event is not exposed via the UAPI -- this is because host responses are on a shared memory buffer of type BLOB_MEM_GUEST [this is the common way to receive responses with virtgpu]. As such, there is no context specific read(..) implementation either -- just a poll(..) implementation. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Acked-by: Nicholas Verne <nverne@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20210921232024.817-12-gurchetansingh@chromium.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-09-29drm/virtio: implement context init: handle VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASKGurchetan Singh
For the Sommelier guest Wayland proxy, it's desirable for the DRM fd to be pollable in response to an host compositor event. This can also be used by the 3D driver to poll events on a CPU timeline. This enables the DRM fd associated with a particular 3D context to be polled independent of KMS events. The parameter VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK specifies the pollable rings. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Acked-by: Nicholas Verne <nverne@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20210921232024.817-11-gurchetansingh@chromium.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-09-29drm/virtio: implement context init: allocate an array of fence contextsGurchetan Singh
We don't want fences from different 3D contexts (virgl, gfxstream, venus) to be on the same timeline. With explicit context creation, we can specify the number of ring each context wants. Execbuffer can specify which ring to use. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Acked-by: Lingfeng Yang <lfy@google.com> Link: http://patchwork.freedesktop.org/patch/msgid/20210921232024.817-10-gurchetansingh@chromium.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-02 03:32:59 +0000